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1. (WO2018080634) THREE-DIMENSIONAL MEMORY DEVICE HAVING NON-UNIFORM SPACING AMONG MEMORY STACK STRUCTURES AND METHOD OF MAKING THEREOF
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Pub. No.: WO/2018/080634 International Application No.: PCT/US2017/049674
Publication Date: 03.05.2018 International Filing Date: 31.08.2017
IPC:
H01L 27/11565 (2017.01) ,H01L 27/1157 (2017.01) ,H01L 27/11582 (2017.01)
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!][IPC code unknown for H01L 27/1157][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
Applicants:
SANDISK TECHNOLOGIES LLC [US/US]; 6900 North Dallas Parkway Suite 325 Plano, Texas 75024, US
Inventors:
MIZUTANI, Yuki; US
OGAWA, Hiroyuki; US
TOYAMA, Fumiaki; US
HIGASHITANI, Masaaki; US
AMANO, Fumitaka; US
FUNAYAMA, Kota; US
UEDA, Akihiro; US
Agent:
RADOMSKY, Leon; US
COHN, Joanna; US
CONNOR, David; US
GAUL, Allison; US
GAYOSO, Tony; US
GEMMEL, Elizabeth; US
GERETY, Todd; US
GILL, Matthew; US
GREGORY, Shaun D.; US
HANSEN, Robert; US
HUANG, Stephen; US
HYAMS, David; US
JOHNSON, Timothy; US
MAZAHERY, Benjamin; US
MURPHY, Timothy; US
NGUYEN, Jaqueline; US
O'BRIEN, Michelle; US
PARK, Byeongju; US
RUTT, Steven; US
SIMON, Phyllis; US
SULSKY, Martin; US
Priority Data:
15/337,23528.10.2016US
Title (EN) THREE-DIMENSIONAL MEMORY DEVICE HAVING NON-UNIFORM SPACING AMONG MEMORY STACK STRUCTURES AND METHOD OF MAKING THEREOF
(FR) DISPOSITIF DE MÉMOIRE TRIDIMENSIONNEL AYANT UN ESPACEMENT NON UNIFORME ENTRE DES STRUCTURES D'EMPILEMENT DE MÉMOIRE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.
(FR) Selon l'invention, un empilement alterné de couches isolantes et de couches de matériau sacrificiel est formé sur un substrat. Des structures d'empilement de mémoire comprenant un film de mémoire et un canal semiconducteur vertical sont formées à travers l'empilement alterné dans une configuration de réseau. Des tranchées arrière s'étendant le long d'une direction longitudinale sont formées à travers l'empilement alterné. Des évidement arrière sont formés par retrait des couches de matériau sacrificiel. Le remplissage des évidements arrière avec des couches électroconductrices peut être effectué sans vides ou avec des vides minimaux en agençant les structures d'empilement de mémoire avec un pas non uniforme. Le pas non uniforme peut être le long de la direction perpendiculaire à la direction longitudinale de telle sorte que la distance voisine la plus proche parmi les structures d'empilement de mémoire est au minimum entre les tranchées arrière. En variante ou en plus, le pas peut être modulé le long de la direction longitudinale pour fournir des régions d'espacement plus larges qui s'étendent perpendiculairement à la direction longitudinale.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)