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1. (WO2018079479) MULTILAYER SUBSTRATE AND METHOD FOR MANUFACTURING SAME
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Pub. No.: WO/2018/079479 International Application No.: PCT/JP2017/038169
Publication Date: 03.05.2018 International Filing Date: 23.10.2017
IPC:
H05K 3/46 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/13 (2006.01) ,H05K 1/11 (2006.01) ,H05K 3/40 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
11
Printed elements for providing electric connections to or between printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
40
Forming printed elements for providing electric connections to or between printed circuits
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
用水 邦明 YOSUI Kuniaki; JP
Agent:
特許業務法人 楓国際特許事務所 KAEDE PATENT ATTORNEYS' OFFICE; 大阪府大阪市中央区農人橋1丁目4番34号 1-4-34, Noninbashi, Chuo-ku, Osaka-shi, Osaka 5400011, JP
Priority Data:
2016-21094127.10.2016JP
Title (EN) MULTILAYER SUBSTRATE AND METHOD FOR MANUFACTURING SAME
(FR) SUBSTRAT MULTICOUCHE ET SON PROCÉDÉ DE FABRICATION
(JA) 多層基板およびその製造方法
Abstract:
(EN) This multilayer substrate (1) is provided with: a first base material (12) having insulating properties; a first interlayer connection conductor (42) formed in the first base material (12); a second base material (13) having insulating properties and contacting the first base material (12); a second interlayer connection conductor (43) formed in the second base material (13) and contacting the first interlayer connection conductor; and an insulation layer (21). The insulation layer (21) is composed of an insulation sheet (20) in which a conductive pattern is not formed, the insulation sheet (20) has an opening (H) that surrounds an interface between the first interlayer connection conductor (42) and the second interlayer connection conductor (43), and the first interlayer connection conductor (42) contacts the second interlayer connection conductor (43) through the opening (H).
(FR) L'invention concerne un substrat multicouche (1) pourvu : d'un premier matériau de base (12) ayant des propriétés isolantes ; d'un premier conducteur de connexion intercouche (42) formé dans le premier matériau de base (12) ; d'un second matériau de base (13) ayant des propriétés isolantes et en contact avec le premier matériau de base (12) ; d'un second conducteur de connexion intercouche (43) formé dans le second matériau de base (13) et en contact avec le premier conducteur de connexion intercouche ; et d'une couche d'isolation (21). La couche d'isolation (21) est composée d'une feuille d'isolation (20) dans laquelle aucun motif conducteur n'est formé, la feuille d'isolation (20) comporte une ouverture (H) qui entoure une interface entre le premier conducteur de connexion intercouche (42) et le second conducteur de connexion intercouche (43), et le premier conducteur de connexion intercouche (42) contacte le second conducteur de connexion intercouche (43) par l'intermédiaire de l'ouverture (H).
(JA) 多層基板(1)は、絶縁性の第1基材(12)と、第1基材(12)に形成された第1層間接続導体(42)と、第1基材(12)に接する絶縁性の第2基材(13)と、第2基材(13)に形成され、第1層間接続導体に接合する第2層間接続導体(43)と、絶縁層(21)を備える。絶縁層(21)は、導体パターンが形成されない絶縁シート(20)で構成され、絶縁シート(20)には、第1層間接続導体(42)と第2層間接続導体(43)との接合面を囲む開口(H)が形成され、第1層間接続導体(42)と第2層間接続導体(43)とは、開口(H)を介して接合する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)