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1. (WO2018078538) VERTICAL TRANSPORT FET DEVICES UTILIZING LOW TEMPERATURE SELECTIVE EPITAXY
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Pub. No.: WO/2018/078538 International Application No.: PCT/IB2017/056610
Publication Date: 03.05.2018 International Filing Date: 25.10.2017
IPC:
H01L 21/28 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504, US
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU, GB (MG)
IBM (CHINA) INVESTMENT COMPANY LIMITED [CN/CN]; 25/F, Pangu Plaza No.27, Central North 4th Ring Road, Chaoyang District Beijing 100101, CN (MG)
Inventors:
MOCHIZUKI, Shogo; US
JAGANNATHAN, Hemanth; US
Agent:
LITHERLAND, David; GB
Priority Data:
15/338,65331.10.2016US
Title (EN) VERTICAL TRANSPORT FET DEVICES UTILIZING LOW TEMPERATURE SELECTIVE EPITAXY
(FR) DISPOSITIFS FET À TRANSPORT VERTICAL UTILISANT UNE ÉPITAXIE SÉLECTIVE À BASSE TEMPÉRATURE
Abstract:
(EN) Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less than 500°C on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500°C for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
(FR) L'invention concerne un dépôt de silicium épitaxial à basse température pour former les régions de source ou de drain supérieures de structures VTFET. Les procédés consistent généralement à faire croître de façon épitaxiale une couche de silicium avec un dopant à une température inférieure à 500 °C sur une première surface et une surface supplémentaire pour former un silicium monocristallin sur la première surface et un silicium polycristallin ou amorphe sur la surface supplémentaire. La couche de silicium à croissance épitaxiale est ensuite exposée à un agent de gravure comprenant du HCl et du germanène à une température inférieure à 500 °C pendant une durée efficace pour retirer sélectivement le silicium polycristallin/amorphe sur la surface supplémentaire et former une région de diffusion de germanium sur et dans une surface externe du silicium monocristallin formé sur la première surface.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)