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1. (WO2018076406) VERTICAL STRUCTURE NONPOLAR LED CHIP ON LITHIUM GALLATE SUBSTRATE AND PREPARATION METHOD THEREFOR
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Pub. No.: WO/2018/076406 International Application No.: PCT/CN2016/105812
Publication Date: 03.05.2018 International Filing Date: 15.11.2016
IPC:
H01L 33/06 (2010.01) ,H01L 33/12 (2010.01) ,H01L 33/32 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
04
with a quantum effect structure or superlattice, e.g. tunnel junction
06
within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
12
with a stress relaxation structure, e.g. buffer layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
26
Materials of the light emitting region
30
containing only elements of group III and group V of the periodic system
32
containing nitrogen
Applicants:
华南理工大学 SOUTH CHINA UNIVERSITY OF TECHNOLOGY [CN/CN]; 中国广东省广州市 天河区五山路381号 No.381 Wushan Road, Tianhe District Guangzhou, Guangdong 510640, CN
Inventors:
李国强 LI, Guoqiang; CN
王文樑 WANG, Wenliang; CN
张子辰 ZHANG, Zichen; CN
Agent:
广州市华学知识产权代理有限公司 GUANGZHOU HUAXUE INTELLECTUAL PROPERTY AGENCY CO., LTD; 中国广东省广州市 天河区五山路381号物资大楼首层 1st Floor, Material Building No.381 Wushan Road Tianhe District, Guangzhou Guangdong 510640, CN
Priority Data:
201610925731.624.10.2016CN
Title (EN) VERTICAL STRUCTURE NONPOLAR LED CHIP ON LITHIUM GALLATE SUBSTRATE AND PREPARATION METHOD THEREFOR
(FR) PUCE DE DEL NON POLAIRE À STRUCTURE VERTICALE SUR UN SUBSTRAT DE GALLATE DE LITHIUM ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 镓酸锂衬底上的垂直结构非极性LED芯片及其制备方法
Abstract:
(EN) Provided are a vertical structure nonpolar LED chip on a lithium gallate substrate and a preparation method therefor. According to the method, LED epitaxial wafers are grown on a lithium gallate substrate, the LED epitaxial wafers comprise a GaN buffer layer grown on the lithium gallate substrate, a non-doped GaN layer on the GaN buffer layer, an n-type doped GaN thin film (5) on the non-doped GaN layer, an InGaN/GaN quantum well (4) on the n-type doped GaN thin film and a p-type doped GaN thin film (3) on the InGaN/GaN quantum well. Then, electrode patterns are prepared on the surfaces of the LED epitaxial wafers by the steps of spin coating, photoetching, developing and cleaning, and an electrode metal is sequentially deposited on the upper surfaces of the epitaxial wafers. Then, the LED epitaxial wafers are transferred to a copper substrate. Then, the original lithium gallate substrate is lift off by an HCl solution, a silicon dioxide protective layer is prepared, the corresponding part of an electrode is exposed, then, SiO2 on the electrode is etched away, and a complete vertical structure LED chip is formed.
(FR) La présente invention concerne une puce de DEL non polaire à structure verticale sur un substrat de gallate de lithium et son procédé de préparation. Selon le procédé, des tranches épitaxiales de DEL sont développées sur un substrat de gallate de lithium, les tranches épitaxiales de DEL comprennent une couche tampon de GaN développée sur le substrat de gallate de lithium, une couche de GaN non dopée sur la couche tampon de GaN, un film mince de GaN dopé de type n (5) sur la couche de GaN non dopée, un puits quantique InGaN/GaN (4) sur le film mince de GaN dopé de type n et un film mince de GaN dopé de type p (3) sur le puits quantique InGaN/GaN. Puis, des motifs d'électrode sont préparés sur les surfaces des tranches épitaxiales de DEL par les étapes de dépôt à la tournette, photogravure, développement et nettoyage, et un métal d'électrode est déposé de manière séquentielle sur les surfaces supérieures des tranches épitaxiales. Ensuite, les tranches épitaxiales de DEL sont transférées vers un substrat en cuivre. Finalement, le substrat de gallate de lithium d'origine est décollé au moyen d'une solution de HCl, une couche de protection de dioxyde de silicium est préparée, la partie correspondante d'une électrode est exposée, puis, du SiO2 sur l'électrode est éliminé par gravure, et une puce de DEL à structure verticale complète est formée.
(ZH) 提供一种镓酸锂衬底上的垂直结构非极性LED芯片及其制备方法,该方法在镓酸锂衬底上生长LED外延片,包括生长在镓酸锂衬底上的GaN缓冲层,在GaN缓冲层上的非掺杂GaN层,在非掺杂GaN层上的n型掺杂GaN薄膜(5),在n型掺杂GaN薄膜上的InGaN/GaN量子阱(4),在InGaN/GaN量子阱上的p型掺杂GaN薄膜(3)。接着在LED外延片表面通过匀胶、光刻、显影、清洗步骤制备电极图案,在外延片上表面依次沉积电极金属。随后将LED外延片转移至铜衬底上。接着用HCl溶液将原有镓酸锂衬底剥离,制备二氧化硅保护层,将电极对应部分暴露出来,再将电极上的SiO 2腐蚀掉,形成完整的垂直结构LED芯片。
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African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)