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1. (WO2018067881) SELECTIVE SIN LATERAL RECESS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/067881 International Application No.: PCT/US2017/055431
Publication Date: 12.04.2018 International Filing Date: 05.10.2017
IPC:
H01L 21/3065 (2006.01) ,H01L 21/67 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
Applicants: APPLIED MATERIALS, INC.[US/US]; 3050 Bowers Avenue Santa Clara, California 95054, US
Inventors: CHEN, Zhijun; US
HUANG, Jiayin; US
WANG, Anchuan; US
INGLE, Nitin; US
Agent: MCCORMICK, Daniel K.; US
BERNARD, Eugene J.; US
Priority Data:
15/288,89807.10.2016US
Title (EN) SELECTIVE SIN LATERAL RECESS
(FR) ÉVIDEMENT LATÉRAL DE SIN SÉLECTIF
Abstract:
(EN) Exemplary methods for laterally etching silicon nitride may include flowing a fluorine-containing precursor and an oxygen-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor and the oxygen-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The methods may also include laterally etching the layers of silicon nitride from sidewalls of the trench while substantially maintaining the layers of silicon oxide. The layers of silicon nitride may be laterally etched less than 10 nm from the sidewalls of the trench.
(FR) Selon la présente invention, des exemples de procédés de gravure latérale de nitrure de silicium (SIN) peuvent comprendre l'écoulement d'un précurseur contenant du fluor et d'un précurseur contenant de l'oxygène dans une région de plasma distante d'une chambre de traitement de semi-conducteur. Ces procédés peuvent comprendre la formation d'un plasma à l'intérieur de la région de plasma distante pour générer des effluents de plasma du précurseur contenant du fluor et du précurseur contenant de l'oxygène. Ces procédés peuvent consister à faire s'écouler les effluents de plasma dans une région de traitement de la chambre de traitement de semi-conducteur. Un substrat peut être positionné à l'intérieur de la région de traitement, et le substrat peut comprendre une tranchée formée à travers des couches empilées comprenant des couches alternées de nitrure de silicium et d'oxyde de silicium. Ces procédés peuvent également comprendre la gravure latérale des couches de nitrure de silicium à partir de parois latérales de la tranchée tout en maintenant sensiblement les couches d'oxyde de silicium. Les couches de nitrure de silicium peuvent être gravées latéralement à moins de 10 nm des parois latérales de la tranchée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)