Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel. For this purpose, the clock output signals from the various independent blocks are first mutually aligned in proper order using a lower speed clock, and subsequently offset from one another such that sampling instances of the various sampler blocks are interleaved. Digitized data words corresponding to common input data and outputted by the various sampler blocks are compared after alignment of the clock output signals to correct additional timing misalignment between the multiple sampler blocks. The digitized data words need only be aligned once or at most infrequently after the clock output signals are aligned, since the additional timing misalignment is caused mainly path delays that are substantially invariant over time.