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1. (WO2018066289) SEMICONDUCTOR ELEMENT SUBSTRATE, ETCHING METHOD, AND ETCHING SOLUTION
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Pub. No.: WO/2018/066289 International Application No.: PCT/JP2017/031845
Publication Date: 12.04.2018 International Filing Date: 04.09.2017
IPC:
H01L 21/308 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/306 (2006.01) ,H01L 21/3065 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
308
using masks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
Applicants:
JSR株式会社 JSR CORPORATION [JP/JP]; 東京都港区東新橋一丁目9番2号 9-2, Higashi-shinbashi 1-chome, Minato-ku, Tokyo 1058640, JP
Inventors:
河本 達慶 KAWAMOTO, Tatsuyoshi; JP
山中 達也 YAMANAKA, Tatsuya; JP
金子 尚史 KANEKO, Hisashi; JP
Agent:
大渕 美千栄 OFUCHI, Michie; JP
布施 行夫 FUSE, Yukio; JP
松本 充史 MATSUMOTO, Mitsufumi; JP
Priority Data:
2016-19560803.10.2016JP
Title (EN) SEMICONDUCTOR ELEMENT SUBSTRATE, ETCHING METHOD, AND ETCHING SOLUTION
(FR) SUBSTRAT D’ÉLÉMENT SEMI-CONDUCTEUR, PROCÉDÉ DE GRAVURE, ET SOLUTION DE GRAVURE
(JA) 半導体素子用基板、エッチング方法、及びエッチング液
Abstract:
(EN) Provided is a nitride semiconductor element manufacturing method wherein an altered layer formed to a nitride semiconductor layer by dry etching can be efficiently removed. A nitride semiconductor element manufactured by the manufacturing method is also provided. A semiconductor element substrate relating to the present invention is characterized in that: the semiconductor element substrate is provided with an AlxGa(1-x)N (0xGa(1-x)N (0
(FR) L'invention concerne un procédé de fabrication d'élément semi-conducteur au nitrure dans lequel une couche modifiée formée sur une couche semi-conductrice au nitrure par gravure sèche peut être efficacement éliminée. L'invention concerne également un élément semi-conducteur au nitrure fabriqué par le procédé de fabrication. Un substrat d'élément semi-conducteur se rapportant à la présente invention est caractérisé en ce que: le substrat d'élément semi-conducteur comprend une couche AlxGa(1-x)N (0<x≤1); et la valeur de MA/MG, c'est-à-dire le rapport entre un contenu en Al (MA) et un contenu en Ga (MG), qui sont obtenues par mesure de la surface de la couche AlxGa(1-x )N (0<x≤1) au moyen d'une spectroscopie photoélectronique à rayons X (XPS), est de 0,45 à 0,55. En outre, un procédé de gravure de couche d'AlGaN se rapportant à la présente invention est caractérisé en ce que la gravure humide est effectuée après la réalisation d'une gravure sèche.
(JA) 窒化物半導体層に対してドライエッチングにより形成された変質層を効率的に除去できる窒化物半導体素子の製造方法を提供する。また、該製造方法により製造された窒化物半導体素子を提供する。 本発明に係る半導体素子用基板は、AlGa(1-x)N(0<x≦1)層を備え、該AlGa1-xN(0<x≦1)層の表面をXPSで測定したAl含有量(MA)とGa含有量(MG)との比MA/MGの値が0.45~0.55であることを特徴とする。また、本発明に係るAlGaN層のエッチング方法は、ドライエッチングした後にウエットエッチングを行うことを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)