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1. WO2018063752 - MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL

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Publication Number WO/2018/063752
Publication Date 05.04.2018
International Application No. PCT/US2017/050044
International Filing Date 05.09.2017
IPC
G06F 13/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
CPC
G06F 1/3203
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
G06F 1/3228
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3206Monitoring of events, devices or parameters that trigger a change in power modality
3228Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
G06F 1/3234
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
G06F 1/3237
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
3237by disabling clock generation or distribution
G06F 1/324
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
324by lowering clock frequency
G06F 1/3243
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
3243Power saving in microcontroller unit
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • RAJWAN, Doron
  • ROTEM, Efraim
  • WEISSMANN, Eliezer
  • ANANTHAKRISHNAN, Avinash N.
  • SHAPIRA, Dorit
Agents
  • GARZA, John C.
  • RICHARDS, Edwin E.
  • TROP, Timothy N.
  • ROZMAN, Mark J.
  • PRUNER JR., Fred G.
  • RIFAI, D'Ann Naylor
Priority Data
15/281,65130.09.2016US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
(FR) BOUCLES MULTI-NIVEAUX POUR COMMANDE DE PROCESSEUR INFORMATIQUE
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Abstract
(EN) In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
(FR) Dans un mode de réalisation, un processeur comprend des coeurs de traitement, et une unité de commande centrale pour : exécuter simultanément une boucle de commande externe et une boucle de commande interne, la boucle de commande externe étant destinée à surveiller le processeur dans son ensemble, et la boucle de commande interne étant destinée à surveiller un premier coeur de traitement inclus dans le processeur ; déterminer, sur la base de la boucle de commande externe, une première action de commande pour le premier coeur de traitement inclus dans le processeur ; déterminer, sur la base de la boucle de commande interne, une seconde action de commande pour le premier coeur de traitement inclus dans le processeur ; sur la base d'une comparaison de la première action de commande et de la seconde action de commande, sélectionner la première action de commande ou la seconde action de commande en tant qu'action de commande sélectionnée ; et appliquer l'action de commande sélectionnée sur le premier coeur de traitement. L'invention concerne également d'autres modes de réalisation.
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