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1. (WO2018063400) MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS
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Pub. No.: WO/2018/063400 International Application No.: PCT/US2016/055023
Publication Date: 05.04.2018 International Filing Date: 30.09.2016
IPC:
H01L 25/18 (2006.01) ,H01L 25/065 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors:
ALEKSOV, Aleksandar; US
ELSHERBINI, Adel A.; US
DARMAWIKARTA, Kristof; US
MAY, Robert A.; US
BOYAPATI, Sri Ranga Sai; US
Agent:
GUGLIELMI, David, L.; US
Priority Data:
Title (EN) MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS
(FR) BOÎTIER MULTI-PUCE À INTERCONNEXIONS HAUTE DENSITÉ
Abstract:
(EN) An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
(FR) L'invention concerne un appareil qui comprend : une pluralité de premiers contacts conducteurs ayant un premier espacement de pas sur une surface de substrat, une pluralité de seconds contacts conducteurs ayant un second espacement de pas sur la surface de substrat, et une pluralité d'interconnexions conductrices disposées à l'intérieur du substrat pour coupler un premier groupement de la pluralité de seconds contacts conducteurs associés à un premier site de puce avec un premier groupement de la pluralité de seconds contacts conducteurs associés à un second site de puce et pour coupler un second groupement de la pluralité de seconds contacts conducteurs associés au premier site de puce avec un second groupement de la pluralité de seconds contacts conducteurs associés au second site de puce, les interconnexions conductrices pour coupler les premiers groupements étant présentes dans une couche du substrat au-dessus des interconnexions conductrices pour coupler les seconds groupements. L'invention se rapporte également à d'autres modes de réalisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)