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1. (WO2018063363) REDUCED TRANSISTOR RESISTANCE USING DOPED LAYER
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/063363 International Application No.: PCT/US2016/054889
Publication Date: 05.04.2018 International Filing Date: 30.09.2016
IPC:
H01L 29/78 (2006.01) ,H01L 29/49 (2006.01) ,H01L 29/66 (2006.01)
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors: HUANG, Cheng-Ying; US
METZ, Matthew V.; US
DEWEY, Gilbert; US
RACHMADY, Willy; US
KAVALIEROS, Jack T.; US
MA, Sean T.; US
Agent: RICHARDS, Edwin E.; US
TROP, Timothy N.; US
ROZMAN, Mark J.; US
GARZA, John C.; US
PRUNER JR., Fred G.; US
RIFAI, D'Ann Naylor; US
Priority Data:
Title (EN) REDUCED TRANSISTOR RESISTANCE USING DOPED LAYER
(FR) RÉSISTANCE DE TRANSISTOR RÉDUITE À L'AIDE D'UNE COUCHE DOPÉE
Abstract: front page image
(EN) An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.
(FR) Un mode de réalisation comprend un transistor comprenant : des première, seconde et troisième couches comprenant chacune un matériau du groupe III-V; un canal inclus dans la deuxième couche, qui se trouve entre les première et troisième couches; et une grille ayant des première et seconde portions de grille; (a) (i) les première et troisième couches étant dopées, (a) (ii) le canal se trouve entre les première et seconde portions de grille et la seconde portion de grille se trouve entre le canal et un substrat, (a) (iii) un premier axe coupe les première, seconde, et troisième couches mais pas la première portion de grille, et (a) (iv) un second axe, parallèle au premier axe, coupe les première et seconde portions de grille et le canal. D'autres modes de réalisation sont décrits ici.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)