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1. (WO2018063337) VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS

Pub. No.:    WO/2018/063337    International Application No.:    PCT/US2016/054818
Publication Date: Fri Apr 06 01:59:59 CEST 2018 International Filing Date: Sat Oct 01 01:59:59 CEST 2016
IPC: H01L 21/768
Applicants: INTEL CORPORATION
Inventors: LIN, Kevin
CHANDHOK, Manish
Title: VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS
Abstract:
Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers. Moreover, the gaps may act to reduce capacitance and thereby increase the performance (circuit timing, power consumption, etc.) of the interconnect.