Mobile |
Deutsch |
Español |
Français |
日本語 |
한국어 |
Português |
Русский |
中文 |
العربية |
PATENTSCOPE
Search International and National Patent Collections
Options
Query
Result
Interface
Office
Translate
«
↓
»
Query Language
All
English
Hebrew
Korean
Spanish
Vietnamese
Arabic
Estonian
Indonesian
Polish
Swedish
Chinese
French
Italian
Portuguese
Swedish
Danish
German
Japanese
Russian
Thai
Stem
Sort by:
Relevance
Pub Date Desc
Pub Date Asc
App Date Desc
App Date Asc
List Length
10
50
100
200
Result List Language
Query Language
Vietnamese
German
Italian
Arabic
Swedish
English
Hebrew
Japanese
Polish
Estonian
Spanish
Portuguese
Russian
Danish
Indonesian
Korean
French
Chinese
Swedish
Thai
Displayed Fields
Application Number
Abstract
Int. Class
Inventor Name
Publication Date
Applicant Name
Image
Chart/Graph
Table
Graph
Group by
None
IPC code
Inventors
Publication Dates
Offices of NPEs
Applicants
Filing Dates
Countries
No of Items/Group
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Download Fields
NPEs
Default Search Form
Simple
Advanced Search
Field Combination
Browse by Week (PCT)
Cross Lingual Expansion
Translator
Default Tab Search Form
Front Page
Any Field
Full Text
ID/Numbers
IPC
Names
Dates
Interface Language
English
Deutsch
Français
Español
日本語
中文
한국어
Português
Русский
Skins
Default
Plain
Blue_Sky
Classic
Deep_Marine
Emerald_Town
Japan_Cherry
Ruby
Wine
Multiple Windows Interface
Tooltip Help
IPC Tooltip Help
Office:
All
All
PCT
Africa
ARIPO
Egypt
Kenya
Morocco
Tunisia
South Africa
Americas
United States of America
Canada
LATIPAT
Argentina
Brazil
Chile
Colombia
Costa Rica
Cuba
Dominican Rep.
Ecuador
El Salvador
Guatemala
Honduras
Mexico
Nicaragua
Panama
Peru
Uruguay
Asia-Europe
Australia
Bahrain
China
Denmark
Estonia
Eurasian Patent Office
European Patent Office
France
Germany
Germany(DDR data)
Israel
Japan
Jordan
Portugal
Russian Federation
Russian Federation(USSR data)
Saudi Arabia
United Arab Emirates
Spain
Republic of Korea
India
United Kingdom
Georgia
Asean
Singapore
Viet Nam
Indonesia
Cambodia
Malaysia
Brunei Darussalam
Philippines
Thailand
WIPO translate (Wipo internal translation tool)
Search
Simple
Advanced Search
Field Combination
Cross Lingual Expansion
Browse
Browse by Week (PCT)
Gazette Archive
Download National Phase Entries
Sequence listing
IPC Green Inventory
Portal to patent registers
Translate
WIPO Translate
WIPO Pearl
Options
Sort
Graph
Show Options
News
PATENTSCOPE News
Login
Login
Account Sign Up
Help
How to Search
User Guide PATENTSCOPE
User Guide: Cross Lingual Expansion
User Guide: ChemSearch
Query Syntax
Fields Definition
Country Code
Data Coverage
PCT applications
PCT national phase entry
National collections
Global Dossier public
FAQ
Feedback&Contact
INID codes
Kind codes
Tutorials
About
Overview
Terms And Conditions
Disclaimer
Home
IP Services
PATENTSCOPE
Machine translation
Wipo Translate
Arabic
German
English
Spanish
French
Japanese
Korean
Portuguese
Russian
Chinese
Google Translate
Bing/Microsoft Translate
Baidu Translate
Arabic
English
French
German
Spanish
Portuguese
Russian
Korean
Japanese
Chinese
...
Italian
Thai
Cantonese
Classical Chinese
1. (WO2018063333) TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS PROCESSED THROUGH CONTACT TRENCHES
PCT Biblio. Data
Description
Claims
National Phase
Notices
Drawings
Documents
«
↓
»
Latest bibliographic data on file with the International Bureau
⇨
Submit observation
PermaLink
PermaLink
Bookmark
Pub. No.:
WO/2018/063333
International Application No.:
PCT/US2016/054806
Publication Date:
05.04.2018
International Filing Date:
30.09.2016
IPC:
H01L 29/78
(2006.01),
H01L 21/768
(2006.01),
H01L 29/73
(2006.01),
H01L 21/8238
(2006.01),
H01L 29/423
(2006.01)
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
73
Bipolar junction transistors
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants:
INTEL CORPORATION
[US/US]; 2200 Mission College Boulevard Santa Clara, California 95054 (US)
Inventors:
GLASS, Glenn A.
; (US).
MURTHY, Anand S.
; (US).
YOUNG, Ian A.
; (US).
AVCI, Uygar E.
; (US)
Agent:
BRODSKY, Stephen I.
; (US)
Priority Data:
Title
(EN)
TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS PROCESSED THROUGH CONTACT TRENCHES
(FR)
TRANSISTORS À EFFET TUNNEL COMPRENANT DES RÉGIONS DE SOURCE/DRAIN TRAITÉES PAR L'INTERMÉDIAIRE DE TRANCHÉES DE CONTACT
Abstract:
(EN)
Techniques are disclosed for forming tunneling transistors including source and drain (S/D) regions processed through contact trenches. The techniques allow for final S/D material formation to be delayed in the process flow, thereby helping to prevent dopant diffusion from that S/D material into the channel region. In addition, in some cases, material bandgap engineering may be used to enhance the ability of tunneling transistor devices, such as tunnel field-effect transistors (TFETs) and Fermi filter FETs (FFFETs), to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate. Such material bandgap engineering can incorporate a material-based band offset component by using different material in the S/D regions to control off-state leakage, to expand upon the limited energy band offset achievable using single-composition material configurations. Increasing the band offset can increase the barrier that carriers must overcome to reach the channel region, thereby reducing off-state leakage.
(FR)
L'invention concerne des Techniques de formation de transistors à effet tunnel comprenant des régions de source et de drain (S/D) traitées par l'intermédiaire de tranchées de contact. Les techniques permettent de retarder la formation de matériau S/D final dans le flux de traitement, ce qui aide à empêcher la diffusion de dopant à partir de ce matériau S/D dans la région de canal. De plus, dans certains cas, une ingénierie de bande interdite de matériau peut être utilisée pour améliorer la capacité de dispositifs à transistors à effet tunnel, tels que des transistors à effet de champ tunnel (TFET) et des FETs de filtre de Fermi (FFFETs), pour résister à des courants de fuite à l'état bloqué de la source au drain (à travers le canal) et de la source à la masse/substrat. Une telle ingénierie de bande interdite de matériau peut incorporer un composant de décalage de bande à base de matériau en utilisant différents matériaux dans les régions S/D pour commander une fuite à l'état bloqué, pour s'étendre sur le décalage de bande d'énergie limitée pouvant être obtenu à l'aide de configurations de matériau à composition unique. L'augmentation du décalage de bande peut augmenter la barrière que les porteuses doivent surmonter pour atteindre la région de canal, ce qui permet de réduire les fuites à l'état bloqué.
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language:
English (
EN
)
Filing Language:
English (
EN
)