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1. (WO2018063324) CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING AN ELECTROLYTIC NICKEL LAYER

Pub. No.:    WO/2018/063324    International Application No.:    PCT/US2016/054778
Publication Date: Fri Apr 06 01:59:59 CEST 2018 International Filing Date: Sat Oct 01 01:59:59 CEST 2016
IPC: H01L 23/48
H01L 23/00
H01L 21/48
Applicants: INTEL CORPORATION
Inventors: SATTIRAJU, Seshu V.
GANESAN, Krishna Prakash
BHATIA, Ashish
SRIRAM, Vinay
MUIRHEAD, John
KOTHARI, Hiten
GUNAWAN, Aloysius A.
ARYASOMAYAJULA, Lavanya
GOWRISHANKAR, Shravan
PATTABHIRAMAN, Sriram
GUHA, Sudipto
Title: CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING AN ELECTROLYTIC NICKEL LAYER
Abstract:
A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.