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1. (WO2018063263) PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VERY HIGH DENSITY (VHD) INTERCONNECT LAYERS

Pub. No.:    WO/2018/063263    International Application No.:    PCT/US2016/054559
Publication Date: Fri Apr 06 01:59:59 CEST 2018 International Filing Date: Fri Sep 30 01:59:59 CEST 2016
IPC: H01L 23/00
H01L 23/48
H01L 23/498
H01L 23/525
Applicants: INTEL CORPORATION
Inventors: PIETAMBARAM, Srinivas V.
BOYAPATI, Sri Ranga Sai
MAY, Robert A.
DARMAWIKARTA, Kristof
SOTO GONZALEZ, Javier
LIM, Kwangmo
Title: PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VERY HIGH DENSITY (VHD) INTERCONNECT LAYERS
Abstract:
A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.