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1. (WO2018063252) METHODS AND APPARATUS TO FORM SILICON-BASED TRANSISTORS ON GROUP III-NITRIDE MATERIALS USING ASPECT RATIO TRAPPING

Pub. No.:    WO/2018/063252    International Application No.:    PCT/US2016/054480
Publication Date: Fri Apr 06 01:59:59 CEST 2018 International Filing Date: Fri Sep 30 01:59:59 CEST 2016
IPC: H01L 29/78
H01L 27/092
H01L 21/8238
Applicants: INTEL CORPORATION
Inventors: RADOSAVLJEVIC, Marko
DASGUPTA, Sansaptak
THEN, Han Wui
Title: METHODS AND APPARATUS TO FORM SILICON-BASED TRANSISTORS ON GROUP III-NITRIDE MATERIALS USING ASPECT RATIO TRAPPING
Abstract:
Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.