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1. (WO2018063191) TECHNIQUES FOR FORMING SCHOTTKY DIODES ON SEMIPOLAR PLANES OF GROUP III-N MATERIAL STRUCTURES
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Pub. No.: WO/2018/063191 International Application No.: PCT/US2016/054189
Publication Date: 05.04.2018 International Filing Date: 28.09.2016
IPC:
H01L 29/66 (2006.01) ,H01L 29/20 (2006.01) ,H01L 29/872 (2006.01) ,H01L 29/808 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
20
including, apart from doping materials or other impurities, only AIIIBV compounds
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
808
with a PN junction gate
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
DASGUPTA, Sansaptak; US
RADOSAVLJEVIC, Marko; US
THEN, Han Wui; US
FISCHER, Paul B.; US
Agent:
MALONEY, Neil F.; US
Priority Data:
Title (EN) TECHNIQUES FOR FORMING SCHOTTKY DIODES ON SEMIPOLAR PLANES OF GROUP III-N MATERIAL STRUCTURES
(FR) TECHNIQUES DE FORMATION DE DIODES SCHOTTKY SUR DES PLANS SEMI-POLAIRES DE STRUCTURES DE MATÉRIAU DU GROUPE III-N
Abstract:
(EN) Techniques are disclosed for forming Schottky diodes on semipolar planes of group Ill-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III- N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode.
(FR) L'invention concerne des Techniques de formation de diodes Schottky sur des plans semi-polaires de structures de matériau de nitrure du groupe III (III-N). Un schéma de sur-croissance épitaxiale latérale (LEO) peut être utilisé pour former les structures de matériau du groupe III-N sur lesquelles des diodes Schottky peuvent ensuite être formées. Le schéma LEO pour former des structures III-N peut comprendre la formation d'un matériau d'isolation de tranchée peu profonde (STI) sur un substrat semi-conducteur, la formation de motifs sur des ouvertures dans le STI, et la croissance du matériau III-N sur le substrat semi-conducteur pour former des structures qui s'étendent à travers et au-dessus des ouvertures STI, par exemple. Une structure III-N peut être formée en n'utilisant qu'une seule ouverture STI, une telle structure III-N pouvant avoir une forme de type prisme triangulaire au-dessus du plan supérieur de la couche STI. Un autre traitement peut consister à former la grille (par exemple, une porte de Schottky) et à relier ensemble des régions de source/drain sur des plans semi-polaires (ou des parois latérales) de la structure III-N pour former une diode Schottky à deux bornes.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)