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1. (WO2018062482) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MOUNTING DEVICE
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Pub. No.: WO/2018/062482 International Application No.: PCT/JP2017/035469
Publication Date: 05.04.2018 International Filing Date: 29.09.2017
IPC:
H01L 21/60 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
株式会社新川 SHINKAWA LTD. [JP/JP]; 東京都武蔵村山市伊奈平2丁目51番地の1 51-1, Inadaira 2-chome, Musashimurayama-shi, Tokyo 2088585, JP
Inventors:
中村 智宣 NAKAMURA Tomonori; JP
前田 徹 MAEDA Toru; JP
Agent:
特許業務法人YKI国際特許事務所 YKI PATENT ATTORNEYS; 東京都武蔵野市吉祥寺本町一丁目34番12号 1-34-12, Kichijoji-Honcho, Musashino-shi, Tokyo 1800004, JP
Priority Data:
2016-19494630.09.2016JP
Title (EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MOUNTING DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN SEMI-CONDUCTEUR ET DISPOSITIF DE MONTAGE
(JA) 半導体装置の製造方法および実装装置
Abstract:
(EN) A mounting method for laminating and mounting a specified target lamination number of semiconductor chips 10 on a substrate 30 includes: a first lamination step for laminating while temporarily crimping one or more semiconductor chips 10 on the substrate 30 to thereby form a first chip laminate body ST1; a first permanent crimping step for applying pressure while heating from the upper side of the first chip laminate body ST1 to thereby collectively and permanently crimp the one or more semiconductor chips 10; a second lamination step for sequentially laminating while temporarily crimping two or more semiconductor chips 10 on the permanently crimped semiconductor chips 10 to thereby form a second chip laminate body ST2; and a second permanent crimping step for applying pressure while heating from the upper side of the second chip laminate body ST2 to thereby collectively and permanently crimp the two or more semiconductor chips 10.
(FR) La présente invention concerne un procédé de montage permettant de stratifier et de monter un nombre spécifié de stratifications cibles de puces semi-conductrices (10) sur un substrat (30), qui comprend : une première étape de stratification consistant à stratifier tout en sertissant temporairement une ou plusieurs puces semi-conductrices (10) sur le substrat (30) de façon à former ainsi un premier corps stratifié de puce (ST1) ; une première étape de sertissage permanent consistant à appliquer une pression pendant le chauffage par le côté supérieur du premier corps stratifié de puce (ST1) de façon à sertir ainsi collectivement et de manière permanente lesdites puces semi-conductrices (10) ; une seconde étape de stratification consistant à stratifier de manière séquentielle tout en sertissant temporairement deux puces semi-conductrices ou plus (10) sur les puces semi-conductrices serties de manière permanente (10) de façon à former ainsi un second corps stratifié de puce (ST2) ; et une seconde étape de sertissage permanent consistant à appliquer une pression pendant le chauffage par le côté supérieur du second corps stratifié de puce (ST2) de façon à sertir ainsi collectivement et de manière permanente les deux puces semi-conductrices ou plus (10).
(JA) 基板30上に、規定の目標積層数の半導体チップ10を積層して実装する実装方法は、前記基板30の上において、1以上の半導体チップ10を、順次、仮圧着しながら積層することで第一チップ積層体ST1を形成する第一積層工程と、前記第一チップ積層体ST1を上側から加熱しつつ加圧することで、前記1以上の半導体チップ10を一括で本圧着する第一本圧着工程と、本圧着された半導体チップ10の上において、2以上の半導体チップ10を、順次、仮圧着しながら積層することで第二チップ積層体ST2を形成する第二積層工程と、前記第二チップ積層体ST2を上側から加熱しつつ加圧することで、前記2以上の半導体チップ10を一括で本圧着する第二本圧着工程と、を含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)