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1. (WO2018061851) ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/061851 International Application No.: PCT/JP2017/033633
Publication Date: 05.04.2018 International Filing Date: 19.09.2017
IPC:
H01L 21/336 (2006.01) ,G02F 1/1368 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/32 (2006.01) ,H01L 29/786 (2006.01) ,H01L 51/50 (2006.01) ,H05B 33/02 (2006.01) ,H05B 33/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
28
including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
32
with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
50
specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
02
Details
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
02
Details
06
Electrode terminals
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
北川 英樹 KITAGAWA Hideki; --
大東 徹 DAITOH Tohru; --
今井 元 IMAI Hajime; --
菊池 哲郎 KIKUCHI Tetsuo; --
鈴木 正彦 SUZUKI Masahiko; --
伊藤 俊克 ITOH Toshikatsu; --
上田 輝幸 UEDA Teruyuki; --
西宮 節治 NISHIMIYA Setsuji; --
原 健吾 HARA Kengo; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2016-18777927.09.2016JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME
(FR) SUBSTRAT À MATRICE ACTIVE ET PROCÉDÉ DE FABRICATION ASSOCIÉ
(JA) アクティブマトリクス基板およびその製造方法
Abstract:
(EN) A pixel region of an active matrix substrate 100 is provided with: a thin film transistor 101 having an oxide semiconductor layer 7; an inorganic insulating layer 11 and an organic insulating layer 12, which cover the thin film transistor; a common electrode 15; a dielectric layer 17 mainly containing silicon nitride; and a pixel electrode 19. The inorganic insulating layer has a laminated structure including a silicon oxide layer and a silicon nitride layer, a pixel electrode 10 is in contact with, in a pixel contact hole, a drain electrode 9, and the pixel contact hole comprises a first opening, a second opening, and a third opening, which are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. The side surface of the first opening and the side surface of the second opening are aligned with each other, and the side surface of the second opening includes: a first portion 121 inclined at a first angle θ1 with respect to the substrate; a second portion 122, which is positioned above the first portion, and which is inclined at a second angle θ2 that is larger than the first angle; and a boundary 120, which is positioned between the first portion and the second portion, and the inclination angle of which discontinuously changes with respect to the substrate.
(FR) Une région de pixel d'un substrat de matrice active 100 comprenant un transistor à couche mince 101 ayant une couche semi-conductrice d'oxyde 7; une couche isolante inorganique 11 et une couche isolante organique 12, qui recouvre le transistor à couche mince; une électrode commune 15; une couche diélectrique 17 contenant principalement du nitrure de silicium; et une électrode de pixel 19. La couche isolante inorganique a une structure stratifiée comprenant une couche d'oxyde de silicium et une couche de nitrure de silicium, une électrode de pixel 10 est en contact avec, dans un trou de contact de pixel, une électrode de drain 9, et le trou de contact de pixel comprend une première ouverture, une seconde ouverture et une troisième ouverture, qui sont formées dans la couche isolante inorganique 11, la couche isolante organique 12 et la couche diélectrique 17, respectivement. La surface latérale de la première ouverture et la surface latérale de la seconde ouverture sont alignées l'une avec l'autre, et la surface latérale de la seconde ouverture comprend: une première partie 121 inclinée selon un premier angle θ1 par rapport au substrat; une seconde partie 122, qui est positionnée au-dessus de la première partie, et qui est inclinée selon un second angle θ2 qui est supérieur au premier angle; et une limite 120, qui est positionné entre la première partie et la seconde partie, et dont l'angle d'inclinaison change de manière discontinue par rapport au substrat.
(JA) アクティブマトリクス基板100の画素領域は、酸化物半導体層7を有する薄膜トランジスタ101と、薄膜トランジスタを覆う無機絶縁層11及び有機絶縁層12と、共通電極15と、窒化シリコンを主に含む誘電体層17と、画素電極19とを備え、無機絶縁層は酸化シリコン層と窒化シリコン層とを含む積層構造を有し、画素電極10は画素コンタクトホール内でドレイン電極9と接し、画素コンタクトホールは、無機絶縁層11、有機絶縁層12および誘電体層17にそれぞれ形成された第1開口部、第2開口部および第3開口部で構成され、第1開口部の側面と第2開口部の側面とは整合し、第2開口部の側面は、基板に対して第1の角度θ1で傾斜した第1部分121と、第1部分の上方に位置し、第1の角度よりも大きい第2の角度θ2で傾斜した第2部分122と、第1部分と第2部分との間に位置し、基板に対する傾斜角度が不連続に変化する境界120とを含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)