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1. (WO2018061523) BONDED SOI WAFER MANUFACTURING METHOD
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Pub. No.: WO/2018/061523 International Application No.: PCT/JP2017/029848
Publication Date: 05.04.2018 International Filing Date: 22.08.2017
IPC:
H01L 21/02 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
信越半導体株式会社 SHIN-ETSU HANDOTAI CO.,LTD. [JP/JP]; 東京都千代田区大手町二丁目2番1号 2-1, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP
Inventors:
石塚 徹 ISHIZUKA Toru; JP
濱 節哉 HAMA Setsuya; JP
Agent:
好宮 幹夫 YOSHIMIYA Mikio; JP
小林 俊弘 KOBAYASHI Toshihiro; JP
Priority Data:
2016-18821627.09.2016JP
Title (EN) BONDED SOI WAFER MANUFACTURING METHOD
(FR) PROCÉDÉ DE FABRICATION DE GALETTE DE SOI LIÉE
(JA) 貼り合わせSOIウェーハの製造方法
Abstract:
(EN) The present invention provides a bonded SOI wafer manufacturing method comprising a step in which a bonded SOI wafer having an oxide film on a back surface thereof is subjected to thermal treatment under argon atmosphere to planarized the surface of the SOI layer. The bonded SOI wafer manufacturing method is characterized in that, when the thermal treatment is performed under argon atmosphere in a batch-type thermal treatment furnace, a silicon wafer is disposed as a dummy wafer between adjacent bonded SOI wafers placed in the batch-type thermal treatment furnace during thermal treatment. According to the SOI wafer manufacturing method provided, an increase in LPD can be suppressed in the step of planarizing the surface of the SOI layer by subjecting the bonded SOI wafer having an oxide film on the back surface thereof to thermal treatment under argon atmosphere using a batch-type thermal treatment furnace.
(FR) La présente invention concerne un procédé de fabrication de galette de SoI liée comprenant une étape dans laquelle une galette de SoI liée ayant un film d'oxyde sur une surface arrière de celle-ci est soumise à un traitement thermique sous atmosphère d'argon pour rendre plane la surface de la couche de SoI. Le procédé de fabrication de galette de SoI liée est caractérisé en ce que, lorsque le traitement thermique est effectué sous atmosphère d'argon dans un four de traitement thermique de type intermittent, une galette de silicium est disposée sous la forme d'une galette factice entre des galettes de SoI liées adjacentes placées dans le four de traitement thermique de type intermittent pendant le traitement thermique. Le procédé de fabrication de galette de SoI selon l'invention permet de supprimer une augmentation du LPD lors de l'étape de planarisation de la surface de la couche de SoI en soumettant la galette de SoI liée sur la face arrière de laquelle se trouve un film d'oxyde à un traitement thermique sous atmosphère d'argon en utilisant un four de traitement thermique de type intermittent.
(JA) 本発明は、裏面に酸化膜を有する貼り合わせSOIウェーハに、アルゴン雰囲気下で熱処理を施してSOI層の表面を平坦化する工程を有する貼り合わせSOIウェーハの製造方法であって、アルゴン雰囲気下での熱処理をバッチ式熱処理炉により行う際に、バッチ式熱処理炉内に収容された隣り合う貼り合わせSOIウェーハの間に、ダミーウェーハとしてシリコンウェーハを配置して熱処理を行うことを特徴とする貼り合わせSOIウェーハの製造方法である。これにより、裏面に酸化膜を有する貼り合わせSOIウェーハにバッチ式熱処理炉によりアルゴン雰囲気下で熱処理を施してSOI層の表面を平坦化する工程において、LPDの増加を抑制することができるSOIウェーハの製造方法が提供される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)