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1. (WO2018060570) STRUCTURE COMPRISING SINGLE-CRYSTAL SEMICONDUCTOR ISLANDS AND PROCESS FOR MAKING SUCH A STRUCTURE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/060570 International Application No.: PCT/FR2017/052529
Publication Date: 05.04.2018 International Filing Date: 21.09.2017
Chapter 2 Demand Filed: 27.03.2018
IPC:
H01L 21/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Applicants:
SOITEC [FR/FR]; Parc Technologique des Fontaines Chemin des Franques 38190 Bernin, FR
Inventors:
SOTTA, David; FR
KONONCHUK, Oleg; FR
BETHOUX, Jean-Marc; FR
Agent:
BREESE, Pierre; FR
Priority Data:
165934329.09.2016FR
Title (EN) STRUCTURE COMPRISING SINGLE-CRYSTAL SEMICONDUCTOR ISLANDS AND PROCESS FOR MAKING SUCH A STRUCTURE
(FR) STRUCTURE COMPRENANT DES ILOTS SEMI-CONDUCTEURS MONOCRISTALLINS, PROCEDE DE FABRICATION D'UNE TELLE STRUCTURE
Abstract:
(EN) The invention relates to a structure (10) for producing at least one active layer made of a III-V material (6), comprising a substrate composed of a carrier (2) having a main face, of a dielectric layer (3) located on the main face of the carrier, and of a plurality of single-crystal semiconductor islands (4) located directly on the dielectric layer (3), the islands having an upper surface in order to serve as seed for the growth of the active layer. According to the invention, the structure comprises a bonding layer (5) located between the single-crystal semiconductor islands (4), directly on the portion of the dielectric layer (3) that is not covered by the islands (4), without masking the upper surface of the islands (4), so that the dielectric layer (3) is no longer exposed to its environment.
(FR) L'invention porte sur une structure (10) pour l'élaboration d'au moins une couche active en matériau III-V (6) comprenant un substrat formé d'un support (2) présentant une face principale, d'une couche diélectrique (3) disposée sur la face principale du support, et d'une pluralité d'îlots semi-conducteurs monocristallins (4) disposée directement sur la couche diélectrique (3), les îlots présentant une surface supérieure pour servir de germe à la croissance de la couche active. Selon l'invention la structure comprend une couche d'accroché (5) disposée entre les îlots semi-conducteurs monocristallins (4), directement sur la portion de la couche diélectrique (3) qui n'est pas recouverte par les îlots (4), sans masquer la surface supérieure des îlots (4), de sorte que la couche diélectrique (3) ne soit plus exposée à son environnement.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)