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Machine translation
1. (WO2018060283) CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2018/060283    International Application No.:    PCT/EP2017/074546
Publication Date: 05.04.2018 International Filing Date: 27.09.2017
IPC:
G06F 1/32 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504 (US).
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU (GB) (MG only)
Inventors: HAESS, Juergen; (US).
PAYER, Stefan; (DE).
LICHTENAU, Cedric; (DE).
SCHELM, Kerstin, Claudia; (DE)
Agent: LITHERLAND, David; (GB)
Priority Data:
15/282,077 30.09.2016 US
Title (EN) CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS
(FR) INHIBITION D'HORLOGE POUR INSTRUCTIONS MULTICYCLES
Abstract: front page image
(EN)A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.
(FR)L'invention concerne un système et un procédé d'inhibition d'horloge pour des instructions multicycles. Par exemple, le procédé comprend l'activation d'une pluralité de blocs logiques qui comprennent un sous-ensemble de blocs logiques multicycles (MC) et un sous-ensemble de blocs logiques en pipeline. Le procédé consiste également à calculer une valeur de calcul de validation précise après une pluralité de cycles d'exécution d'une instruction, et à désactiver un ou plusieurs blocs du sous-ensemble de blocs logiques à plusieurs cycles (MC) sur la base de la valeur de calcul d'activation précise. De plus, au moins le sous-ensemble de blocs logiques en pipeline nécessaires pour calculer l'instruction reste actif.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)