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1. (WO2018059697) OPTOELECTRONIC SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2018/059697 International Application No.: PCT/EP2016/073301
Publication Date: 05.04.2018 International Filing Date: 29.09.2016
IPC:
H01L 33/48 (2010.01) ,H01L 33/56 (2010.01) ,H01L 33/62 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
52
Encapsulations
56
Materials, e.g. epoxy or silicone resin
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
62
Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
Applicants:
OSRAM OPTO SEMICONDUCTORS GMBH [DE/DE]; Leibnizstr. 4 93055 Regensburg, DE
Inventors:
LIM, Choo Kean; MY
NENG, Siang Min; MY
OR, Choon Keat; MY
KOAY, Seong Tak; MY
Agent:
PATENT ATTORNEYS WILHELM & BECK; Prinzenstr. 13 80639 Munich, DE
Priority Data:
Title (EN) OPTOELECTRONIC SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
(FR) BOÎTIER DE PUCE SEMI-CONDUCTEUR OPTOÉLECTRONIQUE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) The scope of the invention is an optoelectronic semiconductor package, comprising an optoelectronic semiconductor chip, which comprises a first contact pad and a second contact pad for applying an electric voltage to the optoelectronic semiconductor chip and a light emitting face. The optoelectronic package further comprises an isolating material adjacent to the optoelectronic semiconductor chip forming a housing of the optoelectronic semiconductor chip. The housing comprises walls. The light emitting face of the optoelectronic semiconductor chip is uncovered by the isolating material. A part of the first contact pad and a part of the second contact pad are free from the isolating material. The first contact pad is arranged at a first wall of the housing, which is opposite to the emitting face. The optoelectronic package further comprises a first contact layer in electrical contact with the first contact pad, which is arranged at the first wall and at a second wall of the housing, extending over a first edge between the first and the second wall of the housing. A second contact layer is in electrical contact with the second contact pad and arranged at a wall of the housing.
(FR) L'invention a pour objet un boîtier semi-conducteur optoélectronique comprenant une puce semi-conductrice optoélectronique, qui comprend un premier plot de contact et un second plot de contact pour appliquer une tension électrique à la puce semi-conductrice optoélectronique et à une face électroluminescente. Le boîtier optoélectronique comprend en outre un matériau isolant adjacent à la puce semi-conductrice optoélectronique formant un boîtier de la puce semi-conductrice optoélectronique. Le boîtier comprend des parois. La face électroluminescente de la puce semi-conductrice optoélectronique est découverte par le matériau isolant. Une partie du premier plot de contact et une partie du second plot de contact sont exemptes du matériau isolant. La premier plot de contact est disposé au niveau d'une première paroi du boîtier, qui est opposée à la face d'émission. Le boîtier optoélectronique comprend en outre une première couche de contact en contact électrique avec le premier plot de contact, qui est disposé au niveau de la première paroi et au niveau d'une seconde paroi du boîtier, s'étendant sur un premier bord entre la première et la seconde paroi du boîtier. Une seconde couche de contact est en contact électrique avec le second plot de contact et disposée au niveau d'une paroi du boîtier.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)