Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018059110) MEMORY DEVICE, METHOD FOR MANUFACTURING SAME, AND ELECTRONIC APPARATUS COMPRISING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/059110 International Application No.: PCT/CN2017/095189
Publication Date: 05.04.2018 International Filing Date: 31.07.2017
IPC:
H01L 27/115 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
Applicants:
中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN/CN]; 中国北京市 朝阳区北土城西路3号 No. 3 Beitucheng West Road, Chaoyang District Beijing 100029, CN
Inventors:
朱慧珑 ZHU, Huilong; US
Agent:
中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.; 中国北京市 海淀区西三环北路87号4-1105室 11/F., Bldg. D International Finance and Economics Center No. 87, West 3rd Ring North Road, Haidian District Beijing 100089, CN
Priority Data:
201610872924.X30.09.2016CN
201710530337.730.06.2017CN
Title (EN) MEMORY DEVICE, METHOD FOR MANUFACTURING SAME, AND ELECTRONIC APPARATUS COMPRISING SAME
(FR) DISPOSITIF DE MÉMOIRE, PROCÉDÉ DE FABRICATION DUDIT DISPOSITIF DE MÉMOIRE, ET APPAREIL ÉLECTRONIQUE COMPORTANT LEDIT DISPOSITIF DE MÉMOIRE
(ZH) 存储器件及其制造方法及包括该存储器件的电子设备
Abstract:
(EN) A memory device, a method for manufacturing the same, and an electronic apparatus comprising the same are provided. The memory device may comprise: forming a plurality of first columnar active regions and a plurality of second columnar active regions extending upwards on a substrate, in which the first and second columnar active regions are respectively arranged as first and second arrays, each of the first columnar active regions comprise alternately stacked source/drain layers and channel layers, the corresponding channel layers of the first columnar active regions are substantially coplanar, the corresponding source/drain layers of the first columnar active regions are substantially coplanar, and each of the second columnar active regions comprises an integral extending active semiconductor layer (1109); stacking a plurality of first memory gates respectively substantially coplanar with the channel layers, the first memory gate stacks respectively surrounding the outer peripheries of the channel layers on corresponding planes; and forming a plurality of second memory gates respectively surrounding the outer peripheries of the second columnar active regions (1107/1105/1103).
(FR) L'invention concerne un dispositif de mémoire, un procédé de fabrication dudit dispositif de mémoire, et un appareil électronique comportant ledit dispositif de mémoire. Le dispositif de mémoire peut consister : à former une pluralité de premières régions actives et une pluralité de secondes régions actives en colonne s'étendant vers le haut sur un substrat, les premières et secondes régions actives en colonne étant respectivement agencées comme des premier et second réseaux, chaque région des premières régions actives en colonne comportant des couches de source/drain empilées en alternance et des couches de canal, les couches de canal correspondantes des premières régions actives en colonne étant sensiblement coplanaires, les couches de source/drain correspondantes des premières régions actives en colonne étant sensiblement coplanaires, et chaque région des secondes régions actives en colonne comportant une couche semi-conductrice active s'étendant d'un seul tenant (1109) ; à empiler une pluralité de premières grilles de mémoire respectivement sensiblement coplanaires avec les couches de canal, les premiers empilements de grilles de mémoire entourant respectivement les périphéries externes des couches de canal sur des plans correspondants ; et à former une pluralité de secondes grilles de mémoire entourant respectivement les périphéries externes des secondes régions actives en colonne (1107/1105/1103).
(ZH) 一种存储器件及其制造方法及包括该存储器件的电子设备。存储器件可以包括:在衬底上形成的向上延伸的多个第一柱状有源区和多个第二柱状有源区,其中,第一、第二柱状有源区分别排列为第一、第二阵列,每一第一柱状有源区包括源/漏层和沟道层的交替堆叠,各第一柱状有源区中相应的沟道层实质上共面,且相应的源/漏层实质上共面,每一第二柱状有源区包括一体延伸的有源半导体层(1109);分别与各沟道层实质上共面的多层第一存储栅堆叠,各层第一存储栅堆叠分别环绕相应平面上各沟道层的外周;环绕各第二柱状有源区外周的多层第二存储栅(1107/1105/1103)。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)