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1. (WO2018059107) SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS COMPRISING SAME
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Pub. No.: WO/2018/059107 International Application No.: PCT/CN2017/095124
Publication Date: 05.04.2018 International Filing Date: 31.07.2017
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES[CN/CN]; No. 3 Beitucheng West Road, Chaoyang District Beijing 100029, CN
Inventors: ZHU, Huilong; US
Agent: CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.; 11/F, Bldg. D International Finance and Economics Center No. 87, West 3rd Ring North Road, Haidian District Beijing 100089, CN
Priority Data:
201610872541.230.09.2016CN
201710531811.830.06.2017CN
Title (EN) SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS COMPRISING SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR, PROCÉDÉ DE FABRICATION DE CELUI-CI ET APPAREIL ÉLECTRONIQUE LE COMPRENANT
(ZH) 半导体器件及其制造方法及包括该器件的电子设备
Abstract:
(EN) A semiconductor device, manufacturing method thereof, and electronic apparatus comprising same. The semiconductor device comprises: a substrate (1001); a cylindrical active region extending vertically upward from the substrate, wherein the active region comprises a first source/drain region in a lower region thereof, a second source/drain region in an upper region thereof, a trench region between the first source/drain region and the second source/drain region and near a surface of a periphery of the active region, and a bulk region (1005) on an inner side of the trench region; and a gate stack formed around a periphery of the trench region.
(FR) L'invention concerne un dispositif semi-conducteur, son procédé de fabrication, et un appareil électronique le comprenant. Le dispositif semi-conducteur comprend : un substrat (1001); une région active cylindrique s'étendant verticalement vers le haut à partir du substrat, la région active comprenant une première région de source/drain dans une région inférieure de celle-ci, une seconde région de source/drain dans une région supérieure de celle-ci, une région de tranchée entre la première région de source/drain et la seconde région de source/drain et à proximité d'une surface d'une périphérie de la région active, et une région de masse (1005) sur un côté interne de la région de tranchée; et un empilement de grille formé autour d'une périphérie de la région de tranchée.
(ZH) 一种半导体器件及其制造方法及包括该器件的电子设备。半导体器件可以包括:衬底(1001);在衬底上竖直延伸的柱状有源区,其中,有源区包括其下部的第一源/漏区、其上部的第二源/漏区、第一源/漏区和第二源/漏区之间靠近其外周表面的沟道区、以及沟道区内侧的体区(1005);以及绕沟道区外周形成的栅堆叠。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)