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1. (WO2018057493) METHOD OF PATTERNING INTERSECTING STRUCTURES
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Pub. No.: WO/2018/057493 International Application No.: PCT/US2017/052190
Publication Date: 29.03.2018 International Filing Date: 19.09.2017
IPC:
H01L 21/027 (2006.01) ,H01L 21/311 (2006.01) ,H01L 29/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
TOKYO ELECTRON LIMITED [JP/JP]; Akasaka Biz Tower 3-1 Alasaka 5-1 Chome, Minato-ku Tokyo, 107-6325, JP
TOKYO ELECTRON U.S. HOLDINGS, INC. [US/US]; 2400 Grove Boulevard Austin, TX 78741, US (JP)
Inventors:
VORONIN, Sergey, A.; US
TALONE, Christopher; US
RANJAN, Alok; US
Agent:
DAVIDSON, Kristi, L.; US
AHRENS, Gregory, F.; US
BENINTENDI, Steven, W.; US
BELLAMY, Glenn, D.; US
ARDIZZONE, Timothy, D.; US
Priority Data:
62/397,77921.09.2016US
Title (EN) METHOD OF PATTERNING INTERSECTING STRUCTURES
(FR) PROCÉDÉ DE FORMATION DE MOTIFS SUR DES STRUCTURES D'INTERSECTION
Abstract:
(EN) Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; altematingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.
(FR) L'invention concerne un procédé de formation de motifs sur un substrat à l'aide d'un schéma d'intégration dans un système de formation de motifs, le procédé consistant : à disposer un substrat dans une chambre de traitement, le substrat ayant une pluralité de structures et un motif, le substrat comprenant une couche sous-jacente et une couche cible, au moins une structure croisant une autre structure, chaque intersection ayant un angle d'intersection et un coin, le schéma d'intégration nécessitant un profil de coin vertical à chaque intersection ; à graver et à nettoyer en alternance et en séquence le substrat pour transférer le motif sur la couche cible et à obtenir un profil de coin vertical cible à chaque intersection ; à commander deux ou plusieurs variables de fonctionnement sélectionnées du schéma d'intégration dans les opérations de gravure et de nettoyage alternées et séquentielles afin d'atteindre des objectifs d'intégration cibles.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)