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1. (WO2018057132) APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT

Pub. No.:    WO/2018/057132    International Application No.:    PCT/US2017/045744
Publication Date: Fri Mar 30 01:59:59 CEST 2018 International Filing Date: Tue Aug 08 01:59:59 CEST 2017
IPC: H01L 27/08
H01L 27/108
H01L 49/02
H01L 23/522
Applicants: MICRON TECHNOLOGY, INC.
Inventors: KONDO, Harunobu
ECHIGOYA, Kenichi
Title: APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT
Abstract:
Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.