Search International and National Patent Collections

1. (WO2018057042) PREFORMED INTERLAYER CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES

Pub. No.:    WO/2018/057042    International Application No.:    PCT/US2016/053830
Publication Date: Fri Mar 30 01:59:59 CEST 2018 International Filing Date: Tue Sep 27 01:59:59 CEST 2016
IPC: H01L 27/06
H01L 21/768
Applicants: INTEL CORPORATION
Inventors: TAN, Elliot N.
Title: PREFORMED INTERLAYER CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES
Abstract:
A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.