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1. (WO2018056694) LOGIC SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/056694 International Application No.: PCT/KR2017/010324
Publication Date: 29.03.2018 International Filing Date: 20.09.2017
IPC:
H01L 29/66 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 21/8228 (2006.01) ,H01L 27/092 (2006.01) ,H01L 29/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8222
Bipolar technology
8228
Complementary devices, e.g. complementary transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Applicants: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION[KR/KR]; 145, Anam-ro Seongbuk-gu Seoul 02841, KR
Inventors: KIM, Sangsig; KR
CHO, Kyoungah; KR
KIM, Min Suk; KR
KIM, Yoon-Joong; KR
WOO, Sola; KR
LIM, Doohyeok; KR
Agent: NURY PATENT LAW FIRM; 4F, 15-5, Teheran-ro 25-gil Gangnam-gu Seoul 06131, KR
Priority Data:
10-2016-012338926.09.2016KR
Title (EN) LOGIC SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR LOGIQUE
(KO) 로직 반도체 소자
Abstract:
(EN) The present invention provides a semiconductor device that performs logic operations. The semiconductor device comprises a plurality of stacked transistors. Each of the transistors comprises: a semiconductor column comprising a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region; a gate electrode disposed to surround the intrinsic region; and a gate insulating film disposed between the gate electrode and the intrinsic region.
(FR) La présente invention concerne un dispositif à semi-conducteur qui effectue des opérations logiques. Le dispositif à semi-conducteur comprend une pluralité de transistors empilés. Chacun des transistors comprend: une colonne de semi-conducteur comprenant une première zone conductrice d'un premier type de conductivité, une seconde zone conductrice d'un second type de conductivité, une zone intrinsèque disposée entre la première zone conductrice et la seconde zone conductrice, et une zone de barrière du premier type de conductivité disposée entre la zone intrinsèque et la deuxième zone conductrice; une électrode de grille disposée de façon à entourer la zone intrinsèque; et une membrane d'isolation de grille disposée entre l'électrode de grille et la zone intrinsèque.
(KO) 본 발명은 논리 연산을 수행하는 반도체 소자를 제공한다. 이 반도체 소자는 반도체 소자는 복수의 적층된 트렌지스터를 포함한다. 상기 트렌지스터 각각은, 제1 도전형의 제1 도전 영역, 제2 도전형의 제2 도전 영역, 상기 제1 도전 영역과 상기 제2 도전 영역 사이에 배치된 진성 영역, 및 상기 진성 영역과 상기 제2 도전 영역 사이에 배치된 제1 도전형의 장벽 영역을 포함하는 반도체 컬럼; 상기 진성 영역을 감싸도록 배치된 게이트 전극; 및 상기 게이트 전극과 상기 진성 영역 사이에 배치된 게이트 절연막을 포함한다.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)