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1. (WO2018056287) SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERTER
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Pub. No.: WO/2018/056287 International Application No.: PCT/JP2017/033823
Publication Date: 29.03.2018 International Filing Date: 20.09.2017
IPC:
H01L 25/07 (2006.01) ,H01L 23/10 (2006.01) ,H01L 23/24 (2006.01) ,H01L 23/28 (2006.01) ,H01L 23/29 (2006.01) ,H01L 23/31 (2006.01) ,H01L 25/18 (2006.01) ,H02M 7/48 (2007.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
10
characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
16
Fillings or auxiliary members in containers, e.g. centering rings
18
Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
24
solid or gel, at the normal operating temperature of the device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
M
APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
7
Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
42
Conversion of dc power input into ac power output without possibility of reversal
44
by static converters
48
using discharge tubes with control electrode or semiconductor devices with control electrode
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
原田 啓行 HARADA, Hiroyuki; JP
原田 耕三 HARADA, Kozo; JP
塩田 裕基 SHIOTA, Hiroki; JP
山口 義弘 YAMAGUCHI, Yoshihiro; JP
山田 浩司 YAMADA, Koji; JP
Agent:
曾我 道治 SOGA, Michiharu; JP
梶並 順 KAJINAMI, Jun; JP
上田 俊一 UEDA, Shunichi; JP
Priority Data:
2016-18406121.09.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERTER
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET CONVERTISSEUR DE PUISSANCE ÉLECTRIQUE
(JA) 半導体装置および電力変換装置
Abstract:
(EN) A semiconductor device which is characterized by comprising: an insulating substrate 52 which has conductor layers 51, 53 on the upper surface and the lower surface, respectively, while having a semiconductor element 4 mounted on the conductor layer 51 on the upper surface; a base plate 1 which is joined to the conductor layer 53 on the lower surface; a case member 2 which surrounds the insulating substrate 52 and is bonded to a surface of the base plate 1, to said surface the conductor layer 53 on the lower surface being joined; a first filler 9 which is a silicone composition filled into a region that is surrounded by the base plate 1 and the case member 2; and a second filler 10 which is a silicone composition that is harder than the first filler 9 and is filled into a region that surrounds the periphery of the insulating substrate 52 below the first filler 9 within the region surrounded by the base plate 1 and the case member 2 and has a height from the base plate 1, which is higher than the upper surface but lower than the joint surface of the conductor layer 51 on the upper surface, said joint surface being joined with the semiconductor element 4.
(FR) La présente invention concerne un dispositif à semi-conducteur caractérisé en ce qu'il comprend : un substrat isolant (52) comportant des couches conductrices (51, 53) sur ses surfaces supérieure et inférieure, respectivement, tandis qu'un élément semi-conducteur (4) est monté sur la couche conductrice (51) sur la surface supérieure ; une plaque de base (1) reliée à la couche conductrice (53) sur la surface inférieure ; un élément boîtier (2) entourant le substrat isolant (52) et lié à une surface de la plaque de base (1), la couche conductrice (53) sur la surface inférieure étant reliée à ladite surface ; une première charge (9), qui est une composition de silicone, introduite dans une région entourée par la plaque de base (1) et l'élément boîtier (2) ; et une seconde charge (10), qui est une composition de silicone plus dure que la première charge (9), introduite dans une région qui entoure la périphérie du substrat isolant (52) au-dessous de la première charge (9) dans la région entourée par la plaque de base (1) et l'élément boîtier (2) et dont la hauteur par rapport à la plaque de base (1) est supérieure à la surface supérieure, mais inférieure à la surface de jonction de la couche conductrice (51) sur la surface supérieure, ladite surface de jonction étant reliée à l'élément semi-conducteur (4).
(JA) 上面と下面とに導体層51、53を有し、上面の導体層51に半導体素子4が搭載された絶縁基板52と、下面の導体層53と接合されたベース板1と、絶縁基板52を囲み、ベース板1の下面の導体層53が接合された面に接着されたケース部材2と、ベース板1とケース部材2とで囲まれた領域に充填されたシリコーン組成物である第一の充填材9と、領域内の第一の充填材9の下部で、絶縁基板52の周縁部を囲み、ベース板1からの高さが上面よりも高く、上面の導体層51の半導体素子4との接合面よりも低い領域に充填され、第一の充填材9よりも硬いシリコーン組成物である第二の充填材10と、を備えたことを特徴とする半導体装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)