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Pub. No.: WO/2018/055666 International Application No.: PCT/JP2016/077661
Publication Date: 29.03.2018 International Filing Date: 20.09.2016
H03K 19/0175 (2006.01)
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Coupling arrangements; Interface arrangements
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
中井 貴之 NAKAI, Takayuki; JP
特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.; 大阪府大阪市北区中之島三丁目2番4号 中之島フェスティバルタワー・ウエスト Nakanoshima Festival Tower West, 2-4, Nakanoshima 3-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
(JA) インターフェース回路
(EN) An interface circuit (10a) is a circuit that receives an input signal VIN having a high potential VIH as a high level and having a low potential VIL as a low level and that outputs an output signal VOUT having a high potential VOH as a high level and having a low potential VOL as a low level. The interface circuit (10a) is provided with a polarity control unit (1a) for controlling whether to in-phase the level of the output signal VOUT with the input signal VIN or whether to invert the polarity of the output signal VOUT with respect to the input signal VIN depending on which of the high potential VIH and the low potential VIL is a GND potential.
(FR) La présente invention concerne un circuit d'interface (10a), lequel est un circuit qui reçoit un signal d'entrée (VIN) ayant un potentiel haut (VIH) en tant que niveau haut et ayant un potentiel bas (VIL) en tant que niveau bas et qui émet un signal de sortie (VOUT) ayant un potentiel haut (VOH) en tant que niveau haut et ayant un potentiel bas (VOL) en tant que niveau bas. Le circuit d'interface (10a) est pourvu d'une unité de commande de polarité (1a) permettant de vérifier s'il faut mettre en phase le niveau du signal de sortie (VOUT) avec le signal d'entrée (VIN) ou s'il faut inverser la polarité du signal de sortie (VOUT) par rapport au signal d'entrée (VIN) selon celui qui est un potentiel GND parmi le potentiel haut (VIH) et le potentiel bas (VIL).
(JA) インターフェース回路(10a)は、高電位VIHをハイレベルとし、低電位VILをローレベルとする入力信号VINを受け、高電位VOHをハイレベルとし、低電位VOLをローレベルとする出力信号VOUTを出力する回路であり、高電位VIHおよび低電位VILのいずれがGND電位であるかに応じて、出力信号VOUTのレベルを入力信号VINと同相にするか、出力信号VOUTを入力信号VINに対して極性を反転させるかを制御する極性制御部(1a)を備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)