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1. (WO2018054122) THIN-FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND ARRAY SUBSTRATE
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Pub. No.: WO/2018/054122 International Application No.: PCT/CN2017/090779
Publication Date: 29.03.2018 International Filing Date: 29.06.2017
IPC:
H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
WANG, Guoying; CN
CHEN, Jiangbo; CN
SONG, Zhen; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201610849619.923.09.2016CN
Title (EN) THIN-FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND ARRAY SUBSTRATE
(FR) TRANSISTOR À COUCHES MINCES, SON PROCÉDÉ DE FABRICATION ET SUBSTRAT DE RÉSEAU
Abstract:
(EN) A method for manufacturing a thin-film transistor is provided, including: forming an active layer (20) over a substrate (10), and performing oxidation treatment to a channel region (23) of the active layer for controlling a carrier concentration in the channel region of the active layer. The active layer having a high carrier concentration is directly formed, and the oxidation treatment can be configured to reduce a carrier concentration of the channel region of the active layer to a level where a gating property of the thin-film transistor is still maintained. In the thin-film transistor manufactured thereby, there is a relatively small contact resistance between a source electrode (61) and a source electrode region (21) of the active layer and between the drain electrode (62) and the drain electrode region (22) of the active layer.
(FR) L'invention concerne un procédé de fabrication d'un transistor à couches minces, consistant à : former une couche active (20) sur un substrat (10), et effectuer un traitement d'oxydation sur une région de canal (23) de la couche active pour commander une concentration de porteurs dans la région de canal de la couche active. La couche active ayant une concentration de porteurs élevée est directement formée, et le traitement d'oxydation peut être configuré pour réduire une concentration de porteurs de la région de canal de la couche active à un niveau où une propriété de portillonnage du transistor à couches minces est encore maintenue. Dans le transistor à couches minces ainsi fabriqué, il existe une résistance de contact relativement faible entre une électrode de source (61) et une région d'électrode de source (21) de la couche active et entre l'électrode de drain (62) et la région d'électrode de drain (22) de la couche active.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)