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1. (WO2018053090) SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS

Pub. No.:    WO/2018/053090    International Application No.:    PCT/US2017/051505
Publication Date: Fri Mar 23 00:59:59 CET 2018 International Filing Date: Fri Sep 15 01:59:59 CEST 2017
IPC: H01L 21/762
H01L 29/06
Applicants: QUALCOMM INCORPORATED
Inventors: XU, Jeffrey, Junhao
YANG, Haining
YUAN, Jun
RIM, Kern
CHIDAMBARAM, Periannan
Title: SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS
Abstract:
Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.