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1. (WO2018052471) A DEGASSING CHAMBER FOR ARSENIC RELATED PROCESSES
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/052471 International Application No.: PCT/US2017/014609
Publication Date: 22.03.2018 International Filing Date: 23.01.2017
IPC:
H01L 21/205 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/67 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Applicants: APPLIED MATERIALS, INC.[US/US]; 3050 Bowers Avenue Santa Clara, California 95054, US
Inventors: BAO, Xinyu; US
YAN, Chun; US
CHUNG, Hua; US
CHU, Schubert S.; US
Agent: PATTERSON, B. Todd; US
TACKETT, Keith M.; US
Priority Data:
62/394,28214.09.2016US
Title (EN) A DEGASSING CHAMBER FOR ARSENIC RELATED PROCESSES
(FR) CHAMBRE DE DÉGAZAGE POUR DES PROCÉDÉS ASSOCIÉS À L'ARSENIC
Abstract:
(EN) Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.
(FR) La présente invention se rapporte de manière générale, dans des modes de réalisation, à la fabrication de circuits intégrés. De façon plus précise, des modes de réalisation de la présente invention se rapportent à un appareil, à des systèmes et à des procédés permettant de réduire le dégazage de substrat. Un substrat est traité dans une chambre de dépôt épitaxial pour déposer un matériau contenant de l'arsenic sur un substrat et, ensuite, transféré jusqu'à une chambre de dégazage pour réduire le dégazage d'arsenic sur le substrat. La chambre de dégazage comprend un panneau de gaz destiné à fournir de l'hydrogène, de l'azote et de l'oxygène et du chlorure d'hydrogène ou du chlore gazeux à la chambre, un support de substrat, une pompe et au moins un mécanisme de chauffage. L'arsenic résiduel ou passager est retiré du substrat de telle sorte que le substrat puisse être retiré de la chambre de dégazage sans disperser l'arsenic dans l'environnement ambiant.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)