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1. (WO2018048713) ELECTROSTATIC CATALYSIS
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Pub. No.: WO/2018/048713 International Application No.: PCT/US2017/049617
Publication Date: 15.03.2018 International Filing Date: 31.08.2017
IPC:
H01M 4/86 (2006.01) ,H01L 29/40 (2006.01) ,C01B 32/15 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
M
PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
4
Electrodes
86
Inert electrodes with catalytic activity, e.g. for fuel cells
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
[IPC code unknown for C01B 32/15]
Applicants:
BECSIS, LLC [US/US]; 2197 Brookwood Drive South Elgin, Illinois 60177, US
Inventors:
BORUTA, Nicholas; US
BORUTA, Michael; US
Agent:
LOMPREY, Jeffrey R.; US
MEARA, Joseph P.; US
LEE-DUTRA, Alice; US
MCPARLAND, James P.; US
EL MENAOUAR, Melissa J.; US
Priority Data:
62/383,68506.09.2016US
Title (EN) ELECTROSTATIC CATALYSIS
(FR) CATALYSE ÉLECTROSTATIQUE
Abstract:
(EN) An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.
(FR) Une électrode ayant une charge incorporée contient un substrat, un premier piège de charge électronique défini au niveau de l'interface d'une première couche isolante et d'une seconde couche isolante ; et une première couche conductrice disposée sur le premier piège de charge électronique ; la première couche conductrice contenant un matériau conducteur configuré pour permettre à un champ électrique externe de pénétrer dans l'électrode à partir du premier piège de charge électronique ; et la première couche isolante n'étant pas la même que la seconde couche isolante.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)