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1. (WO2018047981) SECURE CHIPS WITH SERIAL NUMBERS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/047981 International Application No.: PCT/JP2017/033175
Publication Date: 15.03.2018 International Filing Date: 08.09.2017
Chapter 2 Demand Filed: 21.05.2018
IPC:
H01L 21/027 (2006.01) ,G03F 7/20 (2006.01)
Applicants: MAPPER LITHOGRAPHY IP B.V.[NL/NL]; Computerlaan 15, 2628 XK Delft, NL
Inventors: DE LANGEN, Johannes Cornelis Jacobus; NL
VAN KERVINCK, Marcel Nicolaas Jacobus; NL
KUIPER, Vincent Sylvester; NL
Agent: KURATA, Masatoshi; c/o SUZUYE & SUZUYE, 11th Floor, Celestine Shiba Mitsui Bldg., 3-23-1 Shiba, Minato-ku, Tokyo 1050014, JP
Priority Data:
15/444,39628.02.2017US
62/385,04908.09.2016US
62/458,06213.02.2017US
Title (EN) SECURE CHIPS WITH SERIAL NUMBERS
(FR) PUCES SÉCURISÉES À NUMÉROS DE SÉRIE
Abstract: front page image
(EN) An electronic device comprises a semiconductor chip (100) which comprises a plurality of structures. The chip (100) is a member of a set of chips. The set of chips comprises a plurality of subsets of chips. The chip is a member of only one of the subsets. The structures of the chip include a set of common structures (101) which is the same for all of the chips of the set, and a set of non-common structures (102). The non-common structures (102) of the subset are different from the non-common structures (102) in every other subset. A first portion of the non-common structures (102) is adapted to store or generate a first predetermined value. The first predetermined value is readable from outside of the semiconductor chip (100) by automated reading means. The first portion of the non-common structures (102) is functionally independent from the common structures (101).
(FR) Un dispositif électronique comprend une puce semi-conductrice (100) qui comprend une pluralité de structures. La puce (100) est un élément d'un ensemble de puces. L'ensemble de puces comprend une pluralité de sous-ensembles de puces. La puce est un élément d'un seul des sous-ensembles. Les structures de la puce comprennent un ensemble de structures communes (101) qui est la même pour toutes les puces de l'ensemble, et un ensemble de structures non communes (102). Les structures non communes (102) du sous-ensemble sont différentes des structures non communes (102) dans chaque autre sous-ensemble. Une première portion des structures non communes (102) est conçue pour stocker ou générer une première valeur prédéterminée. La première valeur prédéterminée est lisible depuis l'extérieur de la puce semi-conductrice (100) par des moyens de lecture automatisés. La première portion des structures non communes (102) est fonctionnellement indépendante des structures communes (101).
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)