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1. (WO2018046850) METHODS AND DEVICES FOR BYPASSING THE INTERNAL CACHE OF AN ADVANCED DRAM MEMORY CONTROLLER

Pub. No.:    WO/2018/046850    International Application No.:    PCT/FR2017/052368
Publication Date: Fri Mar 16 00:59:59 CET 2018 International Filing Date: Thu Sep 07 01:59:59 CEST 2017
IPC: G06F 13/16
Applicants: UPMEM
Inventors: ROY, Jean-François
DEVAUX, Fabrice
Title: METHODS AND DEVICES FOR BYPASSING THE INTERNAL CACHE OF AN ADVANCED DRAM MEMORY CONTROLLER
Abstract:
The invention relates to a computing system comprising: a computing device (102) having one or more processor cores (108) under instruction control and a memory controller (112), the memory controller having a cache memory (114); and a memory circuit (104) coupled to the memory controller (112) via a data bus (106A) and an address bus (106B), the memory circuit (104) being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus (106), the computing device (102) being configured to select, for each memory operation accessing the first m-bit memory location, an address among the plurality of first addresses.