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1. (WO2018045167) SUBSTRATE FOR USE IN SYSTEM IN A PACKAGE (SIP) DEVICES
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Pub. No.: WO/2018/045167 International Application No.: PCT/US2017/049611
Publication Date: 08.03.2018 International Filing Date: 31.08.2017
IPC:
H01L 27/04 (2006.01) ,H01L 29/00 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
OCTAVO SYSTEMS LLC [US/US]; 506 West 14th Street, Suite C Austin, TX 78701, US
Inventors:
MURTUZA, Masood; US
WELSH, Erik, James; US
LINDER, Peter; US
FRANTZ, Gene, Alan; US
Agent:
REPPER, George; US
Priority Data:
62/383,13802.09.2016US
Title (EN) SUBSTRATE FOR USE IN SYSTEM IN A PACKAGE (SIP) DEVICES
(FR) SUBSTRAT DESTINÉ À ÊTRE UTILISÉ DANS DISPOSITIFS DE SYSTÈME EN BOÎTIER (SIP)
Abstract:
(EN) A substrate for a SIP is that has a portion of its top surface covered with spaced apart electrically conductive landing pads for electrical connection to components located on the surface and the landing pads serve as interconnection pads for making electrical connections between at least a portion of said pads when interconnected by a segment of bond wire to form at least a portion of the SIP. Methods for use of the universal substrate in SIP system design and manufacture of a SIP.
(FR) Selon la présente invention, une partie de la surface supérieure d'un substrat pour SIP est recouverte de plots de connexion électroconducteurs espacés pour une connexion électrique à des composants situés sur la surface et les plots de connexion servent de plots d'interconnexion pour réaliser des connexions électriques entre au moins une partie desdits plots lorsqu'ils sont interconnectés par un segment de fil de connexion pour former au moins une partie du SIP. L'invention concerne également des procédés d'utilisation du substrat universel dans la conception et la fabrication d'un système SIP.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)