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1. (WO2018044725) TRANSITION GLITCH SUPPRESSION CIRCUIT

Pub. No.:    WO/2018/044725    International Application No.:    PCT/US2017/048667
Publication Date: Fri Mar 09 00:59:59 CET 2018 International Filing Date: Sat Aug 26 01:59:59 CEST 2017
IPC: H03K 5/1252
H03K 5/1254
Applicants: SQUARE, INC.
Inventors: REZAYEE, Afshin
SHIVNARAINE, Ravi
ROUSSON, Alain
YANG, Yue
JULAVITTAYANUKOOL, Kajornsak
Title: TRANSITION GLITCH SUPPRESSION CIRCUIT
Abstract:
A transition glitch suppression circuit (400) can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal (402). The transition glitch suppression circuit has a delay element (404) that can delay the input signal by the time delay to generate a delayed input signal. The transition glitch suppression circuit also has first (406, 412) and second (410, 408) logic circuits that process the input signal and the delayed input signal to generate corresponding outputs. A multiplexer (414) provides the output signal (416) for the suppression circuit by selecting between the output of the first logic circuit (406, 412) and the output of the second logic circuit (410, 408) based on the value of the output signal (416).