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1. (WO2018044717) SELF-BIASING AND SELF-SEQUENCING OF DEPLETION MODE TRANSISTORS
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Pub. No.: WO/2018/044717 International Application No.: PCT/US2017/048621
Publication Date: 08.03.2018 International Filing Date: 25.08.2017
Chapter 2 Demand Filed: 28.06.2018
IPC:
H03F 3/193 (2006.01) ,H03F 1/02 (2006.01) ,H03F 1/52 (2006.01) ,H03F 3/21 (2006.01) ,H03F 3/24 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189
High-frequency amplifiers, e.g. radio frequency amplifiers
19
with semiconductor devices only
193
with field-effect devices
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
02
Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
52
Circuit arrangements for protecting such amplifiers
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
20
Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
21
with semiconductor devices only
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
20
Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
24
of transmitter output stages
Applicants:
MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. [US/US]; 100 Chelmsford Street Lowell, MA 01851, US
Inventors:
ACHIRILOAIE, Benone; US
HOKENSON, Eric; US
Agent:
MCCLELLAN, William, R.; US
Priority Data:
15/250,22029.08.2016US
Title (EN) SELF-BIASING AND SELF-SEQUENCING OF DEPLETION MODE TRANSISTORS
(FR) AUTO-POLARISATION ET AUTO-SÉQUENÇAGE DE TRANSISTORS À MODE D’APPAUVRISSEMENT
Abstract:
(EN) A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.
(FR) Selon la présente invention, un circuit de transistor comprend un transistor comportant une borne de grille et des première et deuxième bornes de conduction, un premier circuit configuré pour convertir un signal d’entrée CA du circuit de transistor en tension de polarisation de grille et pour appliquer la tension de polarisation de grille à la borne de grille du transistor, un deuxième circuit configuré pour convertir le signal d’entrée CA du circuit de transistor en tension de commande, et un circuit de commutation configuré pour appliquer une première tension à la première borne de conduction du transistor en réponse à la tension de commande.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)