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1. (WO2018044494) POROUS SEMICONDUCTOR LAYER TRANSFER FOR AN INTEGRATED CIRCUIT STRUCTURE
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Pub. No.: WO/2018/044494 International Application No.: PCT/US2017/045287
Publication Date: 08.03.2018 International Filing Date: 03.08.2017
Chapter 2 Demand Filed: 06.06.2018
IPC:
H01L 21/78 (2006.01) ,H01L 21/84 (2006.01) ,H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84
the substrate being other than a semiconductor body, e.g. being an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
HAMMOND, Richard; GB
GOKTEPELI, Sinan; US
Agent:
LENKIN, Alan M.; US
LUTZ, Joseph; US
PARTOW-NAVID, Puya; US
FASHU-KANU, Alvin V.; US
Priority Data:
15/256,34102.09.2016US
Title (EN) POROUS SEMICONDUCTOR LAYER TRANSFER FOR AN INTEGRATED CIRCUIT STRUCTURE
(FR) TRANSFERT DE COUCHE DE SEMI-CONDUCTEUR POREUSE POUR UNE STRUCTURE DE CIRCUIT INTÉGRÉ
Abstract:
(EN) An integrated radio frequency (RF) circuit structure may include an active device on a front-side surface of a semiconductor device layer. A backside surface opposite the front-side surface of the semiconductor device layer may be supported by a backside dielectric layer. The integrated RF circuit structure may also include a handle substrate on a front-side dielectric layer that is on a front-side of the active device and a least a portion of the front-side surface of the semiconductor device layer. The integrated RF circuit structure may further include the backside dielectric layer on the backside surface of the semiconductor device layer. The backside dielectric layer may be arranged distal from the front-side dielectric layer.
(FR) Cette invention concerne une structure de circuit intégré radiofréquence (RF) qui peut comprendre un dispositif actif sur une surface avant d'une couche de dispositif à semi-conducteur. Une surface arrière opposée à la surface avant de la couche de dispositif à semi-conducteur peut être supportée par une couche diélectrique arrière. La structure de circuit intégré RF peut également comprendre un substrat de poignée sur une couche diélectrique côté avant qui se trouve sur un côté avant du dispositif actif et au moins une partie de la surface côté avant de la couche de dispositif à semi-conducteur. La structure de circuit intégré RF peut en outre comprendre la couche diélectrique arrière sur la surface arrière de la couche de dispositif à semi-conducteur. La couche diélectrique arrière peut être disposée de manière distale par rapport à la couche diélectrique avant.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)