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1. (WO2018044482) SEGREGATED TEST MODE CLOCK GATING CIRCUITS IN A CLOCK DISTRIBUTION NETWORK OF A CIRCUIT FOR CONTROLLING POWER CONSUMPTION DURING TESTING

Pub. No.:    WO/2018/044482    International Application No.:    PCT/US2017/045081
Publication Date: Fri Mar 09 00:59:59 CET 2018 International Filing Date: Thu Aug 03 01:59:59 CEST 2017
IPC: G06F 1/10
G01R 31/3187
G06F 1/32
Applicants: QUALCOMM INCORPORATED
Inventors: JAIN, Kunal
GHOSH, Moitrayee
BHAT, Anand
FANG, Joseph
Title: SEGREGATED TEST MODE CLOCK GATING CIRCUITS IN A CLOCK DISTRIBUTION NETWORK OF A CIRCUIT FOR CONTROLLING POWER CONSUMPTION DURING TESTING
Abstract:
Segregated test mode clock gating circuits in a clock distribution network of a circuit for controlling power consumption during testing is provided. To reduce power consumption and current-resistance (IR) drop during testing of a circuit, existing clock gating circuits (e.g., clock gating cells (CGCs)) that control the functional mode of circuit blocks in the circuit are additionally test mode gated for hierarchical testing of the circuit. To avoid the need to gate every CGC in the clock distribution network, only certain segregated clock gating circuits in the clock distribution network may be selected for test mode clock gating according to desired testing hierarchy of the circuit. Test mode clock gating of only certain segregated clock gating circuits in a circuit can reduce the number of test gating circuits providing test mode clock gating to mitigate power consumption and area needed for providing selective testing of circuit blocks in the circuit.