Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018044479) SENSE AMPLIFIER CONSTRUCTIONS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/044479 International Application No.: PCT/US2017/045052
Publication Date: 08.03.2018 International Filing Date: 02.08.2017
IPC:
G11C 7/06 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
06
Sense amplifiers; Associated circuits
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; MS 1-525 8000 South Federal Way Boise, ID 83716, US
Inventors:
INGALLS, Charles L.; US
DERNER, Scott J.; US
Agent:
MATKIN, Mark S.; US
GRZELAK, Keith D.; US
LATWESEN, David G.; US
SHAURETTE, James D.; US
HENDRICKSEN, Mark W.; US
Priority Data:
62/381,74531.08.2016US
Title (EN) SENSE AMPLIFIER CONSTRUCTIONS
(FR) STRUCTURES D'AMPLIFICATEUR DE DÉTECTION
Abstract:
(EN) A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.
(FR) L'invention porte sur une structure d'amplificateur de détection comprenant un premier transistor de type n et un second transistor de type n au-dessus du premier transistor de type n. Un troisième transistor de type p est inclus et un quatrième transistor de type p est au-dessus du troisième transistor de type p. Une ligne d'activation de tension inférieure est électriquement couplée à des régions de source/drain de type n qui sont en hauteur entre des grilles respectives des premier et second transistors de type n. Une ligne d'activation de tension plus élevée est électriquement couplée à des régions de source/drain de type p qui sont en hauteur entre des grilles respectives des troisième et quatrième transistors de type p.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)