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1. (WO2018044457) MEMORY CELLS AND MEMORY ARRAYS
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Pub. No.: WO/2018/044457 International Application No.: PCT/US2017/044653
Publication Date: 08.03.2018 International Filing Date: 31.07.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants: MICRON TECHNOLOGY, INC.[US/US]; 8000 South Federal Way Boise, ID 83716, US
Inventors: DERNER, Scott J.; US
SHORE, Michael Amiel; US
Agent: MATKIN, Mark S.; US
GRZELAK, Keith, D.; US
HENDRICKSEN, Mark, W.; US
MATKIN, Mark, S.; US
SHAURETTE, James, D.; US
Priority Data:
62/381,73631.08.2016US
Title (EN) MEMORY CELLS AND MEMORY ARRAYS
(FR) CELLULES DE MÉMOIRE ET MATRICES MÉMOIRE
Abstract:
(EN) Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.
(FR) Certains modes de réalisation comprennent une cellule de mémoire ayant des premier et second transistors et des premier et second condensateurs. Le premier condensateur est déplacé verticalement par rapport au premier transistor. Le premier condensateur a un premier nœud couplé électriquement à une région de source/drain du premier transistor, un second nœud couplé électriquement à une structure de plaque commune, et un premier matériau diélectrique de condensateur entre les premier et second nœuds. Le second condensateur est déplacé verticalement par rapport au second transistor. Le second condensateur a un troisième nœud couplé électriquement à une région de source/drain du second transistor, un quatrième nœud couplé électriquement à la structure de plaque commune, et un second matériau diélectrique de condensateur entre les premier et second nœuds. Certains modes de réalisation comprennent des matrices mémoire comportant des cellules de mémoire 2T-2C.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)