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1. (WO2018044454) MEMORY CELLS AND MEMORY ARRAYS
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Pub. No.: WO/2018/044454 International Application No.: PCT/US2017/044633
Publication Date: 08.03.2018 International Filing Date: 31.07.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way Boise, ID 83716, US
Inventors:
MATHEW, Suraj, J.; US
SINGANAMALLA, Raghunath; US
AHMED, Fawad; US
BROWN, Kris, K.; US
NAIR, Vinay; US
YANG, Gloria; JP
SIMSEK-EGE, Fatma, Arzum; US
TRAN, Diem, Thy N.; US
Agent:
LATWESEN, David, G; US
Priority Data:
62/381,70431.08.2016US
Title (EN) MEMORY CELLS AND MEMORY ARRAYS
(FR) CELLULES MÉMOIRES ET MATRICES MÉMOIRES
Abstract:
(EN) Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.
(FR) Certains modes de réalisation de la présente invention comprennent une cellule mémoire ayant des premier, deuxième et troisième transistors, les deuxième et troisième transistors étant déplacés verticalement l'un par rapport à l'autre. La cellule mémoire comporte un pilier semi-conducteur s'étendant le long des deuxième et troisième transistors, le pilier semi-conducteur contenant des régions de canal et des régions de source/drain des deuxième et troisième transistors. Un condensateur peut être couplé électriquement entre une région de source/drain du premier transistor et une grille du second transistor.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)