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1. (WO2018044453) MEMORY CELLS AND MEMORY ARRAYS
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CLAIMS

I/we claim,

1. A memory cell comprising:

a first transistor supported by a semiconductor base; and second and third transistors above the first transistor and vertically stacked one atop the other.

2. The memory cell of claim 1 wherein a semiconductor material pillar extends along gates of the second and third transistors and comprises source/drain regions and channel regions of the second and third transistors,

3. The memory cell of claim 1 wherein the first transistor comprises a gate that extends downwardly into the semiconductor base, and comprises source/drain regions extending into the semiconductor base.

4. The memory cell of claim 1 comprising a charge-storage device electrically coupled with a source/drain region of the first transistor, and electrically coupled with a gate of the second transistor.

5. The memory cell of claim 4 wherein the charge- storage device is a capacitor extending downwardly into the semiconductor base.

6. The memory cell of claim 4 wherein the charge- storage device is a capacitor extending between the source/drain region of the first transistor and the gate of the second transistor.

7. The memory cell of claim 4 wherein the charge- storage device is a capacitor between a channel region of the second transistor and the gate of the second transistor.

8. The memory cell of claim 1 wherein the charge- storage device is a capacitor comprising dielectric material of the second transistor.

9. A memory cell comprising first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions, the second transistor having third and fourth source/drain regions, and the third transistor having fifth and sixth source/drain regions; wherein the memory cell includes a pillar of semiconductor material extending through the second and third transistors, and which includes the third, fourth, fifth and sixth source/drain regions as well as channel regions of the second and third transistors.

10. The memory cell of claim 9 comprising a first bitline under the second transistor and electrically coupled with the first source/drain region, and comprising a second bitline above the third transistor and electrically coupled with the sixth source/drain region.

11. The memory cell of claim 10 comprising a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor.

12. The memory cell of claim 11 wherein the capacitor extends downwardly to below a gate of the first transistor.

13. The memory cell of claim 11 wherein the capacitor extends between the second source/drain region and the gate of the second transistor.

14. The memory cell of claim 11 wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor.

15. A memory cell, comprising:

first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions electrically coupled to one another through a first channel region, the second transistor having third and fourth source/drain regions electrically coupled to one another through a second channel region, the third transistor having fifth and sixth source/drain regions electrically coupled to one another through a third channel region; the fourth and fifth source/drain regions being electrically coupled to one another;

a read bitline above the third transistor and electrically coupled with the sixth source/drain region;

a write bitline adjacent the first transistor and electrically coupled with the first source/drain region;

a write wordline which includes a gate of the first transistor; a read wordline which includes a gate of the third transistor; and a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor.

16. The memory cell of claim 15 wherein the fourth and fifth source/drain regions overlap one another within a semiconductor pillar; and wherein the second and third channel regions are also within said semiconductor pillar.

17. The memory cell of claim 15 wherein the capacitor extends downwardly to below a gate of the first transistor.

18. The memory cell of claim 15 wherein the capacitor extends between the second source/drain region of the first transistor and the gate of the second transistor.

19. The memory cell of claim 15 wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor.

20. The memory cell of claim 15 wherein the gate of the third transistor is configured to have at least one bent region where the gate of the third transistor couples with the read wordline, and one or more extension regions that extend along the third channel region from said at least one bent region; and wherein the gate of the third transistor and the one or more extension regions together form a substantially T-shaped configuration, substantially shelf-shaped configuration or substantially U-shaped configuration.

21. An apparatus comprising a semiconductor base and a plurality of memory cells, each of the plurality of memory cells comprising:

a first transistor including first and second source/drain regions formed in the semiconductor base, a first channel region therebetween and a first gate controlling the first channel region, the first gate being electrically connected to a first word line; and

a second transistor including third and fourth source/drain regions, a second channel region therebetween and a second gate controlling the second channel region, the third and fourth source/drain regions and the second channel region being vertically disposed with one another between a first bit line and a common plate over the semiconductor base, and the second gate being electrically coupled to the second source/drain region of the first transistor.

22. The apparatus of claim 21, wherein each of the plurality of memory cells further comprises a third transistor disposed above the second transistor, the third transistor including fifth and sixth source/drain regions vertically disposed with one another and a third channel region therebetween, the fifth source/drain region electrically coupled with the fourth source/drain region.

23. The apparatus of claim 22, wherein each of the plurality of memory cells further comprises a semiconductor pillar over the semiconductor base, and the semiconductor pillar including first, second, third, fourth and fifth portions serving as the third source/drain region, the second channel region, the fourth source/drain region, the third channel region and the sixth source/drain region, respectively, the third portion of the semiconductor pillar further serving as the fifth source/drain region.

24. The apparatus of claim 22, wherein the second channel region is larger than the third channel region in length.

25. The apparatus of claim 21, wherein each of the plurality of memory cells further comprises a capacitor electrically coupled with the second source/drain region of the first transistor.

26. The apparatus of claim 25, wherein the capacitor extends downwardly to below the first gate of the first transistor.

27. The apparatus of claim 25, wherein the capacitor extends between the second source/drain region of the first transistor and the second gate of the second transistor.