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1. (WO2018044453) MEMORY CELLS AND MEMORY ARRAYS
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Pub. No.: WO/2018/044453 International Application No.: PCT/US2017/044611
Publication Date: 08.03.2018 International Filing Date: 31.07.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; (a Corporation of the State of Delaware) 8000 South Federal Way Boise, ID 83716, US
Inventors:
MATHEW, Suraj, J.; US
BROWN, Kris, K.; US
SINGANAMALLA, Raghunath; US
NAIR, Vinay; US
AHMED, Fawad; US
SIMSEK-EGE, Fatma, Arzum; US
TRAN, Diem Thy, N.; US
Agent:
MATKIN, Mark, S.; US
Priority Data:
62/381,68531.08.2016US
Title (EN) MEMORY CELLS AND MEMORY ARRAYS
(FR) CELLULES DE MÉMOIRE ET MATRICES DE MÉMOIRE
Abstract:
(EN) Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
(FR) Des modes de réalisation de la présente invention comprennent une cellule de mémoire comportant un premier transistor soutenu par une base semi-conductrice, et comportant des deuxième et troisième transistors au-dessus du premier transistor et empilés verticalement l'un au-dessus de l'autre. Certains modes de réalisation comprennent une cellule de mémoire comportant des premier, deuxième et troisième transistors. Le troisième transistor est au-dessus du deuxième transistor, et les deuxième et troisième transistors sont au-dessus du premier transistor. Le premier transistor comporte des première et deuxième régions de source/drain, le deuxième transistor comporte des troisième et quatrième régions de source/drain et le troisième transistor comporte des cinquième et sixième régions de source/drain. Une ligne de bits de lecture est couplée à la sixième région de source/drain. Une ligne de bits d'écriture est couplée à la première région de source/drain. Une ligne de mots d'écriture comprend une grille du premier transistor. Une ligne de mots de lecture comprend une grille du troisième transistor. Un condensateur est couplé à la deuxième région de source/drain et à une grille du deuxième transistor.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)