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1. (WO2018044383) LEVEL-SHIFTER WITH DEFINED POWER-UP STATE AND INCREASED DENSITY
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/044383 International Application No.: PCT/US2017/039323
Publication Date: 08.03.2018 International Filing Date: 26.06.2017
Chapter 2 Demand Filed: 09.12.2017
IPC:
H03K 3/356 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
Applicants: QUALCOMM INCORPORATED[US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors: PARK, Dongmin; US
PARK, Jong Min; US
LEUNG, Lai Kan; US
Agent: HALLMAN, Jonathan W.; US
Priority Data:
15/253,68331.08.2016US
Title (EN) LEVEL-SHIFTER WITH DEFINED POWER-UP STATE AND INCREASED DENSITY
(FR) DISPOSITIF DE RÉTABLISSEMENT DU NIVEAU ZÉRO À ÉTAT DE MISE SOUS TENSION DÉFINI ET À DENSITÉ ACCRUE
Abstract:
(EN) A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered through a pair of head-switch transistors. A pair of pull-down transistors function to flip a binary state for the one-sided NMOS latch.
(FR) Cette invention concerne un dispositif de rétablissement du niveau zéro dont les dispositifs peuvent tous être dimensionnés de manière approximativement égale mais un état de mise sous tension connu est fourni lors de la mise sous tension du fait que le dispositif de rétablissement du niveau zéro est formé au moyen d'un verrou NMOS à un seul côté. Le verrou NMOS à un seul côté est alimenté au moyen d'une paire de transistors de commutation de tête. Une paire de transistors de rappel vers le niveau bas fonctionne de sorte à faire basculer un état binaire pour le verrou NMOS à un seul côté.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)