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1. (WO2018043643) ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE PROVIDED WITH ACTIVE MATRIX SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/043643 International Application No.: PCT/JP2017/031356
Publication Date: 08.03.2018 International Filing Date: 31.08.2017
IPC:
G09F 9/30 (2006.01) ,G02F 1/1345 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1345
Conductors connecting electrodes to cell terminals
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
西村 淳 NISHIMURA Jun; --
原 義仁 HARA Yoshihito; --
近間 義雅 CHIKAMA Yoshimasa; --
中田 幸伸 NAKATA Yukinobu; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2016-17155202.09.2016JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE PROVIDED WITH ACTIVE MATRIX SUBSTRATE
(FR) SUBSTRAT DE MATRICE ACTIVE ET DISPOSITIF D'AFFICHAGE MUNI D'UN SUBSTRAT DE MATRICE ACTIVE
(JA) アクティブマトリクス基板およびアクティブマトリクス基板を備えた表示装置
Abstract:
(EN) This active matrix substrate (1001) is provided with a plurality of TFTs (10Q) for inspection arranged in a non-display region (900) and an inspection circuit (200) which contains the plurality of TFTs (10Q) for inspection. At least some of the plurality of TFTs (10Q) for inspection are arranged within a semiconductor chip mounting region (R) where a semiconductor chip is to be mounted. Each one of the plurality of TFTs (10Q) for inspection comprises: a semiconductor layer; a lower gate electrode (FG) which is arranged on the substrate-side surface of the semiconductor layer, with a gate insulating layer being interposed therebetween; an upper gate electrode (BG) which is arranged on another semiconductor layer surface that is on the reverse side of the substrate-side surface, with an insulating layer being interposed therebetween, said insulating layer containing a first insulating layer; and a source electrode and a drain electrode, which are connected to the semiconductor layer.
(FR) La présente invention concerne un substrat (1001) de matrice active comportant une pluralité de TFT (10Q) servant à l'inspection, disposés dans une région (900) hors affichage, et un circuit (200) d'inspection qui contient la pluralité de TFT (10Q) servant à l'inspection. Au moins une partie de la pluralité de TFT (10Q) servant à l'inspection est agencée à l'intérieur d'une région (R) de montage de puce à semi-conducteur où une puce à semi-conducteur est appelée à être montée. Chaque TFT de la pluralité de TFT (10Q) servant à l'inspection comporte: une couche semi-conductrice; une électrode de grille inférieure (FG) qui est disposée sur la surface côté substrat de la couche semi-conductrice, une couche d'isolation de grille étant interposée entre celles-ci; une électrode de grille supérieure (BG) qui est disposée sur une autre surface de couche semi-conductrice située du côté opposé à la surface côté substrat, une couche d'isolation étant interposée entre celles-ci, ladite couche d'isolation contenant une première couche d'isolation; et une électrode source et une électrode de drain, qui sont reliées à la couche semi-conductrice.
(JA) アクティブマトリクス基板(1001)は、非表示領域(900)に配置された複数の検査用TFT(10Q)と、複数の検査用TFT(10Q)を含む検査回路(200)とを備え、複数の検査用TFT(10Q)の少なくとも一部は、半導体チップが搭載される半導体チップ搭載領域(R)内に配置され、複数の検査用TFT(10Q)のそれぞれは、半導体層と、半導体層の基板側に、ゲート絶縁層を介して配置された下部ゲート電極(FG)と、半導体層の基板と反対側に、第1絶縁層を含む絶縁層を介して配置された上部ゲート電極(BG)と、半導体層に接続されたソース電極およびドレイン電極とを含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)