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1. (WO2018043317) OPTICAL MODULATOR
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Pub. No.: WO/2018/043317 International Application No.: PCT/JP2017/030468
Publication Date: 08.03.2018 International Filing Date: 25.08.2017
IPC:
G02F 1/025 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
015
based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
025
in an optical waveguide structure
Applicants:
日本電信電話株式会社 NIPPON TELEGRAPH AND TELEPHONE CORPORATION [JP/JP]; 東京都千代田区大手町一丁目5番1号 5-1,Otemachi 1-chome,Chiyoda-ku, Tokyo 1008116, JP
Inventors:
開 達郎 HIRAKI,Tatsurou; JP
松尾 慎治 MATSUO,Shinji; JP
Agent:
山川 茂樹 YAMAKAWA,Shigeki; JP
小池 勇三 KOIKE,Yuzo; JP
山川 政樹 YAMAKAWA,Masaki; JP
Priority Data:
2016-16651829.08.2016JP
Title (EN) OPTICAL MODULATOR
(FR) MODULATEUR OPTIQUE
(JA) 光変調器
Abstract:
(EN) This optical modulator is provided with: a p-type first semiconductor layer (102) that is formed on a cladding layer (101); an insulating layer (103) that is formed on the first semiconductor layer (102); and an n-type second semiconductor layer (104) that is formed on the insulating layer (103). The first semiconductor layer (102) is configured from silicon or silicon-germanium; and the second semiconductor layer (104) is configured from a group III-V compound semiconductor that is composed of three or more materials.
(FR) Ce modulateur optique comprend : une première couche semi-conductrice de type p (102) qui est formée sur une couche de gainage (101); une couche isolante (103) qui est formée sur la première couche semi-conductrice (102); et une seconde couche semi-conductrice de type n (104) qui est formée sur la couche isolante (103). La première couche semi-conductrice (102) est configurée à partir de silicium ou de silicium-germanium; et la seconde couche semi-conductrice (104) est configurée à partir d'un semi-conducteur composé du groupe III-V qui est composé de trois matériaux ou plus.
(JA) クラッド層(101)の上に形成されたp型の第1半導体層(102)と、第1半導体層(102)の上に形成された絶縁層(103)と、絶縁層(103)の上に形成されたn型の第2半導体層(104)とを備える。第1半導体層(102)は、シリコンまたはシリコンゲルマニウムから構成され、第2半導体層(104)は、3つ以上の材料からなるIII-V族化合物半導体から構成されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)