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1. (WO2018043140) SOLID-STATE IMAGING ELEMENT AND ELECTRONIC DEVICE
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Pub. No.: WO/2018/043140 International Application No.: PCT/JP2017/029494
Publication Date: 08.03.2018 International Filing Date: 17.08.2017
IPC:
H01L 27/146 (2006.01) ,H04N 5/369 (2011.01) ,H04N 5/374 (2011.01) ,H04N 9/07 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
9
Details of colour television systems
04
Picture signal generators
07
with one pick-up device only
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
松本 晃 MATSUMOTO Akira; JP
田舎中 博士 TAYANAKA Hiroshi; JP
Agent:
西川 孝 NISHIKAWA Takashi; JP
稲本 義雄 INAMOTO Yoshio; JP
Priority Data:
2016-16759130.08.2016JP
Title (EN) SOLID-STATE IMAGING ELEMENT AND ELECTRONIC DEVICE
(FR) ÉLÉMENT D'IMAGERIE À SEMI-CONDUCTEURS ET DISPOSITIF ÉLECTRONIQUE
(JA) 固体撮像素子、および電子装置
Abstract:
(EN) The present technique relates to: a solid-state imaging element which enables the reduction in the chip size of a CIS that uses an organic photoelectric conversion film; and an electronic device. A solid-state imaging element according to one embodiment of the present invention is characterized by being provided with: first and second substrates that are laminated on each other; and a first organic photoelectric conversion film that is formed on the first substrate. This solid-state imaging element is also characterized in that a latch circuit is formed on the second substrate. The present technique is applicable, for example, to a backside-illuminated CIS.
(FR) La présente technique concerne : un élément d'imagerie à semi-conducteurs qui permet la réduction de la taille de puce d'un CIS qui utilise un film de conversion photoélectrique organique; et un dispositif électronique. Un élément d'imagerie à semi-conducteurs selon un mode de réalisation de la présente invention est caractérisé en ce qu'il comprend: des premier et second substrats qui sont stratifiés l'un sur l'autre; et un premier film de conversion photoélectrique organique qui est formé sur le premier substrat. Cet élément d'imagerie à semi-conducteurs est également caractérisé en ce qu'un circuit de verrouillage est formé sur le second substrat. La présente technique est applicable, par exemple, à un dispositif CIS rétro-éclairé.
(JA) 本技術は、有機光電変換膜を用いたCISのチップサイズを小型化することができるようにする固体撮像素子、および電子装置に関する。 本技術の第1の側面である固体撮像素子は、積層されている第1および第2基板と、前記第1基板の上に形成されている第1有機光電変換膜とを備え、前記第2基板には、Latch回路が形成されていることを特徴とする。本技術は、例えば、裏面照射型のCISに適用できる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)